NCV3020BDR2G ON Semiconductor, NCV3020BDR2G Datasheet - Page 9

• Manufacturer Part Number: NCV3020BDR2G
• Description: IC PWM CTLR SYNC 8SOIC
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCV3020BDR2G

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 670kHz
• Duty Cycle: 80%
• Voltage - Supply: 4.7 V ~ 28 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

OVERVIEW
mode, pulse width modulated, (PWM) synchronous buck
converter. It drives high−side and low−side N−channel power
MOSFETs. The NCP3020 incorporates an internal boost
circuit consisting of a boost clamp and boost diode to provide
supply voltage for the high side MOSFET gate driver. The
NCP3020 also integrates several protection features including
input undervoltage lockout (UVLO), output undervoltage
(OUV), output overvoltage (OOV), adjustable high−side
current limit (I
provides a high gain error signal from Vout which is
compared to the internal 1.5 V pk-pk ramp signal to set the
duty cycle converter using the PWM comparator. The high
side switch is turned on by the positive edge of the clock
cycle going into the PWM comparator and flip flop
following a non-overlap time. The high side switch is turned
off when the PWM comparator output is tripped by the
modulator ramp signal reaching a threshold level
established by the error amplifier. The gate driver stage
incorporates fixed non− overlap time between the high−side
The NCP3020A/B operates as a 300/600 kHz, voltage
The operational transconductance amplifier (OTA)
0.7 V
0 V
OTA Output
Internal Reference Voltage
SET
and I
Internal Ramp
LIM
), and thermal shutdown (TSD).
Figure 21. Soft−Start Details
DETAILED DESCRIPTION
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24 Voltage Steps
9
and low−side MOSFET gate drives to prevent cross
conduction of the power MOSFET’s.
POR and UVLO
input Undervoltage Lockout (UVLO) that inhibits the internal
logic and the output stage from operating until V
respective predefined voltage levels (4.3 V typical).
Startup and Shutdown
begins its startup process. Closed−loop soft−start begins
after a 400 ms delay wherein the boost capacitor is charged,
and the current limit threshold is set. During the 400 ms delay
the OTA output is set to just below the valley voltage of the
internal ramp. This is done to reduce delays and to ensure a
consistent pre−soft−start condition. The device increases the
internal reference from 0 V to 0.6 V in 24 discrete steps
while maintaining closed loop regulation at each step. Each
step contains 64 switching cycles. Some overshoot may be
evident at the start of each step depending on the voltage
loop phase margin and bandwidth. The total soft−start time
is 6.8 ms for the NCP3020A and 4.4 ms for the NCP3020B.
The device contains an internal Power On Reset (POR) and
Once V
25 mV Steps
CC
crosses the UVLO rising threshold the device
0.6 V
CC
reaches its