NCV3020BDR2G ON Semiconductor, NCV3020BDR2G Datasheet - Page 13

• Manufacturer Part Number: NCV3020BDR2G
• Description: IC PWM CTLR SYNC 8SOIC
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCV3020BDR2G

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 670kHz
• Duty Cycle: 80%
• Voltage - Supply: 4.7 V ~ 28 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Soft−Start Current limit
inrush current to charge the output capacitance. The DAC
reference is set back to its normal value after soft−start has
completed.
V
V
high−side transistor on−time. Proper snubber design and
keeping the ratio of ripple current and load current in the
10−30% range can help alleviate this as well.
Current Limit
cycle and subsequently half of another cycle T
for negative inductor current that might have caused
negative potentials on the output. Subsequently the power
MOSFETs are both turned off and a 4 soft−start time period
wait passes before another soft−start cycle is attempted.
I
the equation below:
I
Where:
L = Inductance (H)
I
R
R
V
V
F
ave
AveTRIP
SET
SW
SW
SW
SET
DS(on)
IN
OUT
During soft−start the I
The I
A current limit trip results in completion of one switching
The average load trip current versus R
vs Trip Point
= Input Voltage (V)
Ringing
= 13 mA
= Switching Frequency (Hz)
voltage ringing that extends beyond the 1/2 point of the
= Gate to Source Resistance (W)
= Output Voltage (V)
Vsense
Itrip Ref
Limit
+
= On Resistance of the HS MOSFET (W)
I
set
R
block can lose accuracy if there is excessive
DS(on)
R
set
*
1/4
Ton−2
1
4
¾
SET
Ton−1
Each switching cycle’s Ton is counted in 10 nS time steps. The 3/4 sample time
1/2
V
value is doubled to allow for
IN
3/4
* V
No Trip:
Vsense < I
L
value is held and used for the following cycle’s limit sample time
OUT
SET
3/4 Point Determined by
Figure 27. I
trip
V
V
value is shown
OUT
Trip:
Vsense > I
Ref at 3/4 Point
IN
on
Prior Cycle
to account
F
(eq. 2)
http://onsemi.com
1
SW
Limit
trip
Ref at 3/4 Point
Trip Point Description
13
Boost Clamp Functionality
between the BST and V
the high and low−side gate driver voltage. This clamp circuit
limits the driver voltage to typically 7.5 V when V
otherwise this internal regulator is in dropout and typically
V
and acts as a switching diode. A simplified diagram of the
boost circuit is shown in Figure 28. While the switch node
is grounded, the sampling circuit samples the voltage at the
boost pin, and regulates the boost capacitor voltage. The
sampling circuit stores the boost voltage while the V
high and the linear regulator output transistor is reversed
biased.
IN
The boost circuit requires an external capacitor connected
The boost circuit regulates the gate driver output voltage
1/4
Ton−1
− 1.25 V.
¾
Ton
1/2
3/4
8.9V
Figure 28. Boost Circuit
Current Level 1
Sampling
Switch
Circuit
SW
pins to store charge for supplying
VIN
BST
VSW
LSDR
Current Level 2
IN
> 9 V,
SW
is