PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 75

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1
14.1.1
Pericom Semiconductor
CONFIGURATION REGISTER 1 AND 2
VENDOR ID REGISTER – OFFSET 00h
Bit
15:0
Secondary Latency
Chassis Number
Upstream (S1 or S2 to P) Memory Limit
Reserved
31-24
Timer
Function
Vendor ID
Hot Swap Control and Status
Prefetchable Memory Limit
Upstream Memory Control
Master Timeout Counter
I/O Limit Upper 16-bit
Secondary Status
Arbiter Control
Bridge Control
Memory Limit
Device ID
Reserved
Reserved
Status
Upstream (S1 or S2 to P) Memory Limit Upper 32-bit
Upstream (S1 or S2 to P) Memory Base Upper 32-bit
Secondary Successful Memory Write Counter
Secondary Successful Memory Read Counter
Primary Successful Memory Write Counter
Subordinate Bus
Primary Successful Memory Read Counter
Type
R/O
Secondary Successful I/O Write Counter
Secondary Successful I/O Read Counter
Header Type
Slot Number
Primary Successful I/O Write Counter
Class Code
Primary Successful I/O Read Counter
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Reserved
Number
23-16
Prefetchable Limit Upper 32-bit
Prefetchable Base Upper 32-bit
Hot Swap Switch Time Slot
Description
Identifies Pericom as vendor of this device. Hardwired as 12D8h.
Sampling Timer
Retry Counter
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Primary Latency Timer
Secondary Bus
Upstream (S1 or S2 to P) Memory Base
Next Pointer
Next Pointer
I/O Limit
Number
15-8
Prefetchable Memory Base
Diagnostic / Chip Control
Secondary Clock Control
3-PORT PCI-TO-PCI BRIDGE
I/O Base Upper 16-bit
November 2005 - Revision 1.01
Memory Base
ECP Pointer
Port Option
Vendor ID
Command
Reserved
Reserved
Primary Bus Number
P_SERR# Event
Cache Line Size
Capability ID
Capability ID
Revision ID
I/O Base
Disable
7-0
PI7C7300D
Address
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
4Ch
50h
54h
58h
5Ch
60h
64h
68h
6Ch
70h
74h
78h
7Ch
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h-AFh
B0h
B4h-BFh
C0h
D0h-FFh