PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 59

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BIT
Pericom Semiconductor
Table 7-3 SETTING PRIMARY INTERFACE DATA PARITY ERROR DETECTED BIT
Table 7-4 SETTING SECONDARY INTERFACE DATA PARITY ERROR DETECTED
Table 7-3 shows setting data parity detected bit in the primary interface’s status register.
This bit is set under the following conditions:
X = don’t care
Table 7-4 shows setting the data parity detected bit in the status register of secondary
interface. This bit is set under the following conditions:
X= don’t care
Primary Data
Parity Bit
0
0
1
0
0
0
1
0
0
0
1
0
Secondary
Detected Parity
Detected Bit
0
1
0
0
0
1
0
0
0
1
0
0
PI7C7300D must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary
interface, must be set.
The P_PERR# signal is detected asserted or a parity error is detected on the primary
bus.
The PI7C7300D must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
The S_PERR# signal is detected asserted or a parity error is detected on the
secondary bus.
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Page 59 of 107
Direction
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
3-PORT PCI-TO-PCI BRIDGE
Bus Where Error
Was Detected
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Was Detected
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
November 2005 - Revision 1.01
Primary /
Secondary Parity
Error Response
Bits
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
Primary /
Secondary Parity
Error Response
Bits
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
PI7C7300D