PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 26

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.6.4
4.6.5
Pericom Semiconductor
Table 4-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES
bytes of write data with valid byte enable bits are compared. If any of the byte enable bits
are turned off (driven HIGH), the corresponding byte of write data is not compared.
If the initiator repeats the write transaction before the data has been transferred to the
target, PI7C7300D returns a target retry to the initiator. PI7C7300D continues to return a
target retry to the initiator until write data is delivered to the target, or until an error
condition is encountered. When the write transaction is repeated, PI7C7300D does not
make a new entry into the delayed transaction queue. Section 4.9.3.1 provides detailed
information about how PI7C7300D responds to target termination during delayed write
transactions.
PI7C7300D implements a discard timer that starts counting when the delayed write
completion is at the head of the delayed transaction completion queue. The initial value
of this timer can be set to the retry counter register offset 78h.
If the initiator does not repeat the delayed write transaction before the discard timer
expires, PI7C7300D discards the delayed write completion from the delayed transaction
completion queue. PI7C7300D also conditionally asserts P_SERR# (see Section 7.4).
WRITE TRANSACTION ADDRESS BOUNDARIES
PI7C7300D imposes internal address boundaries when accepting write data. The aligned
address boundaries are used to prevent PI7C7300D from continuing a transaction over a
device address boundary and to provide an upper limit on maximum latency. PI7C7300D
returns a target disconnect to the initiator when it reaches the aligned address boundaries
under conditions shown in Table 4–3.
Note 1. Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the
configuration space.
BUFFERING MULTIPLE WRITE TRANSACTIONS
PI7C7300D continues to accept posted memory write transactions as long as space for at
least one DWORD of data in the posted write data buffer remains. If the posted write
data buffer fills before the initiator terminates the write transaction, PI7C7300D returns a
target disconnect to the initiator.
Type of Transaction
Delayed Write
Posted Memory Write
Posted Memory Write
Posted Memory Write and
Invalidate
Posted Memory Write and
Invalidate
bit = 0
Condition
All
Memory write disconnect control
Memory write disconnect control
bit = 1
Cache line size ≠ 1, 2, 4, 8, 16
Cache line size = 1, 2, 4, 8, 16
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(1)
(1)
3-PORT PCI-TO-PCI BRIDGE
Aligned Address Boundary
4KB aligned address boundary
Disconnects at cache line boundary
4KB aligned address boundary
Cache line boundary if posted memory
write data FIFO does not have enough
space for the cache line
Disconnects after one data transfer
November 2005 - Revision 1.01
PI7C7300D