PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 57

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pericom Semiconductor
Similarly, during upstream posted write transactions, when PI7C7300D responds as a
target, it detects a data parity error on the initiator (secondary) bus, the following events
occur:
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of S_PERR#, the following events occur:
During upstream write transactions, when a data parity error is reported on the target
(primary) bus by the target’s assertion of P_PERR#, the following events occur:
Assertion of P_SERR# is used to signal the parity error condition when the initiator does
not know that the error occurred. Because the data has already been delivered with no
errors, there is no other way to signal this information back to the initiator. If the parity
error has forwarded from the initiating bus to the target bus, P_SERR# will not be
asserted.
PI7C7300D asserts S_PERR# two cycles after the data transfer, if the parity error
response bit is set in the bridge control register of the secondary interface.
PI7C7300D sets the parity error detected bit in the status register of the secondary
interface.
PI7C7300D captures and forwards the bad parity condition to the primary bus.
PI7C7300D completes the transaction normally.
PI7C7300D sets the data parity detected bit in the status register of secondary
interface, if the parity error response bit is set in the bridge control register of the
secondary interface.
PI7C7300D asserts P_SERR# and sets the signaled system error bit in the status
register, if all the following conditions are met:
-
-
-
-
-
PI7C7300D sets the data parity detected bit in the status register, if the parity error
response bit is set in the command register of the primary interface.
PI7C7300D asserts P_SERR# and sets the signaled system error bit in the status
register, if all the following conditions are met:
-
-
-
-
The SERR# enable bit is set in the command register.
The posted write parity error bit of P_SERR# event disable register is not set.
The parity error response bit is set in the bridge control register of the secondary
interface.
The parity error response bit is set in the command register of the primary
interface.
PI7C7300D has not detected the parity error on the primary (initiator) bus which
the parity error is not forwarded from the primary bus to the secondary bus.
The SERR# enable bit is set in the command register.
The parity error response bit is set in the bridge control register of the secondary
interface.
The parity error response bit is set in the command register of the primary
interface.
PI7C7300D has not detected the parity error on the secondary (initiator) bus
which the parity error is not forwarded from the secondary bus to the primary
bus.
Page 57 of 107
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
PI7C7300D