AD9814JRRL Analog Devices Inc, AD9814JRRL Datasheet - Page 14

• Manufacturer Part Number: AD9814JRRL
• Description: IC CCD SIGNAL PROC 14BIT 28-SOIC
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9814JRRL

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 80mA
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 10MSPS
• Operating Supply Voltage (min): 3/4.75V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Resolution: 14b
• Supply Current: 64/1.8mA
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SOIC W
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Not Compliant

AD9814
APPLICATIONS INFORMATION
Circuit and Layout Recommendations
The recommended circuit configuration for 3-Channel CDS
mode operation is shown in Figure 15. The recommended input
coupling capacitor value is 0.1 F (see Circuit Operation section
for more details). A single ground plane is recommended for the
AD9814. A separate power supply may be used for DRVDD,
the digital driver supply, but this supply pin should still be
decoupled to the same ground plane as the rest of the AD9814.
The loading of the digital outputs should be minimized, either
by using short traces to the digital ASIC, or by using external
digital buffers. To minimize the effect of digital transients during
major output code transitions, the falling edge of CDSCLK2
CLOCK INPUTS
DATA OUTPUTS
0.1 F
CLOCK INPUTS
DATA OUTPUTS
0.1 F
+5V/3V
+5V/3V
Figure 15. Recommended Circuit Configuration, 3-Channel CDS Mode
Figure 16. Recommended Circuit Configuration, 3-Channel SHA Mode
(Analog Inputs Sampled with Respect to Ground)
3
8
3
8
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CDSCLK1
CDSCLK2
ADCCLK
OEB
DRVDD
DRVSS
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
1
2
3
4
5
6
7
8
9
CDSCLK1
CDSCLK2
ADCCLK
OEB
DRVDD
DRVSS
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
AD9814
AD9814
OFFSET
SLOAD
SDATA
AVDD
CAPB
AVDD
AVSS
CAPT
AVSS
SCLK
VING
OFFSET
VINR
VINB
CML
–14–
SLOAD
SDATA
AVDD
CAPB
AVDD
AVSS
CAPT
AVSS
SCLK
VING
VINR
VINB
CML
28
27
26
25
24
23
22
21
20
19
18
17
16
15
should occur coincident with or before the rising edge of
ADCCLK (see Figures 1 through 4 for timing). All 0.1 F
decoupling capacitors should be located as close as possible to
the AD9814 pins. When operating in single channel mode, the
unused analog inputs should be grounded.
Figure 16 shows the recommended circuit configuration for 3-
Channel SHA mode. All of the above considerations also apply
for this configuration, except that the analog input signals are
directly connected to the AD9814 without the use of coupling
capacitors. The analog input signals must already be dc-biased
between 0 V and 4 V (see the Circuit Operation section for
more details).
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+5V
+5V
0.1 F
0.1 F
3
3
SERIAL INTERFACE
SERIAL INTERFACE
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
+5V
+
+5V
RED INPUT
GREEN INPUT
BLUE INPUT
+
0.1 F
10 F
RED INPUT
GREEN INPUT
BLUE INPUT
10 F
0.1 F
0.1 F
0.1 F
0.1 F
1.0 F
REV. 0