LM1246DKBNANOPB National Semiconductor, LM1246DKBNANOPB Datasheet - Page 34

• Manufacturer Part Number: LM1246DKBNANOPB
• Manufacturer: National Semiconductor

Specifications of LM1246DKBNANOPB

• Lead Free Status / Rohs Status: Compliant

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Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bits 4–0
Bits 7–5
Bit 0
Bit 1
Control Register Definitions
Frame Control Register 2:
Character Font Access Register:
On-Screen Display Enable. The On-Screen Display will be disabled when this bit is a zero. When this bit is a one
the On-Screen Display will be enabled. This controls both Window 1 and Window 2.
Display Window 1 Enable. When this bit and Bit 0 of this register are both ones, Display Window 1 is enabled. If
either bit is a zero, then Display Window 1 will be disabled.
Display Window 2 Enable. When this bit and Bit 0 of this register are both ones, Display Window 2 is enabled. If
either bit is a zero, then Display Window 2 will be disabled.
Clear Display Page RAM. Writing a one to this bit will result in setting all of the Display Page RAM values to zero.
This bit is automatically cleared after the operation is complete. This bit is initially asserted by default at power up,
and will clear itself back to zero shortly after. Thus, the default value is one only momentarily, and then will remain
zero until manually asserted again or until the power is cycled.
Transparent Disable. When this bit is a zero, a palette color of black (i.e., color palette look-up table value of 0x00)
in the first 8 palette look-up table address locations (i.e., ATT0–ATT7) will be interpreted as transparent. When this
bit is a one, the color will be interpreted as black.
Fade In/Out Enable. When this bit is a 1, the OSD Fade In/Fade Out function is enabled. When this bit is a 0, the
function is disabled.
Auto Size Enable. When this bit is a 1, the Auto Size function is enabled. Once video detection and measurement
is completed, the bit will automatically clear itself back to 0.
Half Tone Disable. When this bit is a 1, the OSD Half Tone Transparency function is disabled. When this bit is a 0,
the half tone transparency is enabled.
Blinking Period. These five bits set the blinking period of the blinking feature, which is determined by mulitiplying
the value of these bits by 8, and then multiplying the result by the vertical field rate.
Pixels per Line. These three bits determine the number of pixels per line of OSD characters. See Table 27. OSD
Pixels per Line which gives the maximum horizontal scan rate. Also see Table 3. OSD Register Recommendations
since the maximum recommended scan rate is also a function of the PLLFREQRNG register, 0x843E[1:0].
This is the Color Bit Plane Selector. This bit must be set to 0 to read or write a two-color attribute from the range
0x0000 to 0x2FFF. When reading or writing four-color attributes from the range 0x3000 to 0x3FFF, this bit is set to
0 for the least significant plane and to 1 for the most significant plane. It is also required to set this bit to read the
individual bit planes of the four color character fonts in 0x3000 to 0x3FFF and 0x7000 to 0x7FFF.
This is the Character/Attribute Selector. This applies to reads from the Display Page RAM (address range
0x8000–0x81FF). When a 0, the character code is returned and when a 1, the attribute code is returned.
Bits 7–5
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
X
Pixels per Line
PL[2:0]
X
TABLE 27. OSD Pixels per Line
X
Reserved
(Continued)
CHARFONTACC (0x8402)
FRMCTRL2 (0x8401)
1024 pixels per line
1088 pixels per line
1152 pixels per line
704 pixels per line
768 pixels per line
832 pixels per line
896 pixels per line
960 pixels per line
Description
X
34
X
Blink Period
BP[4:0]
X
Select
ATTR
Max Horizontal Frequency (kHz)
FONT4
Plane
110
110
110
110
110
108
102
96