LM1246DKBNANOPB National Semiconductor, LM1246DKBNANOPB Datasheet - Page 20

• Manufacturer Part Number: LM1246DKBNANOPB
• Manufacturer: National Semiconductor

Specifications of LM1246DKBNANOPB

• Lead Free Status / Rohs Status: Compliant

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OSD Generator Operation
WINDOWS
Two separate windows can be opened, utilizing the data
stored in the page RAM. Each window has its own horizontal
and vertical start position, although the second window
should be horizontally spaced at least two character spaces
away from the first window, and should never overlap the
first window when both windows are on. The OSD window
must be placed within the active video.
OSD VIDEO DAC
The OSD DAC is controlled by the 9-bit (3x3 bits) OSD video
information coming from the pixel serializer look-up table.
The look-up table in the OSD palette is programmed to
FIGURE 16. Block Diagram of OSD DACs
(Continued)
FIGURE 15. Bank Addressing
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select 4 color levels out of 8 linearly spaced levels per
channel. The OSD DAC is shown in Figure 16, where the
gain is programmable by the 2-bit OSD contrast register, in 4
stages to give the required OSD signal. The OSD DACs use
the reference voltage, V
OSD VIDEO TIMING
The OSD analog signal then goes to the switch, shown in
Figure 16 and Figure 1 where the timing control switches
from input video to OSD and back again as determined by
the control registers. This is also where horizontal and ver-
tical blanking are also inserted at their appropriate intervals.
REF
, to bias the OSD outputs.
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