M69000 Asiliant Technologies, M69000 Datasheet - Page 106

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

CR09
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 09h
7
6
&+,36
Scanning
Double
7
Double Scanning
0: Disables double scanning. The clock to the row scan counter is equal to the horizontal scan rate.
This is the normal setting for many of the standard VGA modes and all of the extended modes.
1: Enables double scanning. The clock to the row scan counter is divided by 2. This is normally
used to allow CGA-compatible modes that have only 200 scanlines of active video data to be
displayed as 400 scanlines (each scanline is displayed twice).
Line Compare Bit 9
This bit provides the most significant bit of a 10-bit value that specifies the scanline at which the
memory address counter restarts at the value of 0. Bit 4 of the Overflow Register (CR07) supplies
the second most significant bit and bits 7-0 of the Line Compare Register (CR18) supply the 8 least
significant bits.
Normally, this 10-bit value is set to specify a scanline after the last scanline of the active display
area. When this 10-bit value is set to specify a scanline within the active display area, it causes that
scanline and all subsequent scanlines in the active display area to display video data starting at the
very first byte of the frame buffer. The result is what appears to be a screen split into a top and
bottom part, with the image in the top part being repeated in the bottom part.
When used in cooperation with the Start Address High Register (CR0C) and the Start Address Low
Register (CR0D), it is possible to create a split display but with the top and bottom parts displaying
different data, as described earlier. The top part will display whatever data exists in the frame buffer
starting at the address specified in the two start address registers (CR0C and CR0D) while the
bottom part will display whatever data exists in the frame buffer starting at the first byte of the frame
buffer.
69000 Databook
Maximum Scanline Register
Line Cmp
Bit 9
6
Start Bit 9
Vert Blnk
5
Subject to Change Without Notice
CRT Controller Registers
4
3
Maximum Scanline
2
Revision 1.3 8/31/98
1
0
9-13