DS26514GN+ Maxim Integrated Products, DS26514GN+ Datasheet - Page 75

• Manufacturer Part Number: DS26514GN+
• Description: IC TXRX T1/E1/J1 4PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26514GN+

• Number Of Drivers/receivers: 4/4
• Protocol: Ethernet
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(TLS2)
Transmit Interrupt Mask Register 2
(TIM2)
Transmit HDLC-64 FIFO Buffer
Available
(TFBA)
Transmit HDLC-64 FIFO (THF)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex); where n = 2 to 4 for Framers 2 to 4.
9.10.1.1
Control of the transmit and receive FIFOs is accomplished via the Receive HDLC-64 FIFO Control (RHFC) and
Transmit HDLC-64 FIFO Control (THFC) registers. The FIFO Control registers set the watermarks for the FIFO.
When the receive FIFO fills above the high watermark, the RHWM bit (RRTS5.1) will be set. RHWM and TLWM
are real-time bits and will remain set as long as the FIFO’s write pointer is above the watermark. When the transmit
FIFO empties below the low watermark, the TLWM bit in the
and will remain set as long as the transmit FIFO’s write pointer is below the watermark. If enabled, this condition
can also cause an interrupt via the INTB pin.
If the receive HDLC FIFO does overrun, the current packet being processed is dropped and the receive FIFO will
be emptied . The packet status bits in
9.10.1.2
The lower 7 bits of the Receive HDLC Packet Bytes Available Register (RHPBA) indicates the number of bytes (0
to 64) that can be read from the receive FIFO. The value indicated by this register informs the host as to how many
bytes can be read from the receive FIFO without going past the end of a message. This value will refer to one of
four possibilities, the first part of a packet, the continuation of a packet, the last part of a packet, or a complete
packet. After reading the number of bytes indicated by this register the host then checks the HDLC status registers
for detailed message status.
If the value in the
the MSB of the RHPBA register will return a value of 1. This indicates that the host can safely read the number of
bytes returned by the lower 7 bits of the RHPBA register, but there is no need to check the information register
since the packet has not yet terminated (successfully or otherwise).
9.10.1.3
RRTS5, RLS5, and
(or is occurring), the appropriate bit in one of these registers will be set to a one. Some of the bits in these registers
are latched and some are real-time bits that are not latched. This section contains register descriptions that list
which bits are latched and which are real-time. With the latched bits, when an event occurs and a bit is set to a
one, it will remain set until the user reads and clears that bit. The bit will be cleared when a 1 is written to the bit
and it will not be set again until the event has occurred again. The real-time bits report the current instantaneous
conditions that are occurring and the history of these bits is not latched.
Like the other latched status registers, the user will follow a read of the status bit with a write. The byte written to
the register will inform the device which of the latched bits the user wishes to clear (the real-time bits are not
affected by writing to the status register). The user will write a byte to one of these registers, with a one in the bit
positions he or she wishes to clear and a zero in the bit positions he or she does not wish to clear.
The HDLC status registers
signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the HDLC
interrupt mask registers
pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused
the interrupt to occur.
Rev: 101608
REGISTER
HDLC-64 FIFO Control
Receive Packet Bytes Available
HDLC-64 Status and Information
RHPBA
TLS2
RIM5
provide status information for the HDLC controller. When a particular event has occurred
register refers to the beginning portion of a message or continuation of a message, then
RLS5
and TIM2. Interrupts will force the INTB signal low when the event occurs. The INTB
and
RRTS5
TLS2
and RLS5.5 (ROVR) indicate an overrun.
have the ability to initiate a hardware interrupt via the INTB output
ADDRESSES
FRAMER 1
1A1h
1B3h
1B4h
TRTS2
Interrupt Mask for the Latched Status
Indicates the number of bytes that can be
written into the Transmit FIFO
Transmit HDLC FIFO
register will be set. TLWM is a real-time bit
DS26514 4-Port T1/E1/J1 Transceiver
FUNCTION
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