PIC18F2520-I/ML Microchip Technology Inc., PIC18F2520-I/ML Datasheet - Page 60
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PIC18F2520-I/ML
Manufacturer Part Number
PIC18F2520-I/ML
Description
28 QFN 6x6mm TUBE, 32 KB Flash, 1536 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2520-IML.pdf
(412 pages)
Specifications of PIC18F2520-I/ML
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1K Bytes
Input Output
25
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Temperature Range
–40 to 125 °C
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2520-I/ML
Manufacturer:
MICROCHI
Quantity:
20 000
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PIC18F2420/2520/4420/4520
5.2.3
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSb = 0). To maintain alignment
with instruction boundaries, the PC increments in steps
of 2 and the LSb will always read ‘0’ (see Section 5.1.1
“Program Counter”).
Figure 5-4 shows an example of how instruction words
are stored in the program memory.
FIGURE 5-4:
5.2.4
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction spec-
ifies a special form of NOP. If the instruction is executed
in proper sequence – immediately after the first word –
the data in the second word is accessed and used by
EXAMPLE 5-4:
DS39631E-page 58
CASE 1:
Object Code
CASE 2:
Object Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
INSTRUCTIONS IN PROGRAM
MEMORY
TWO-WORD INSTRUCTIONS
Instruction 1:
Instruction 2:
Instruction 3:
INSTRUCTIONS IN PROGRAM MEMORY
TWO-WORD INSTRUCTIONS
Program Memory
Byte Locations
MOVLW
GOTO
MOVFF
Source Code
TSTFSZ
Source Code
MOVFF
ADDWF
TSTFSZ
MOVFF
ADDWF
055h
0006h
123h, 456h
→
REG1
REG1, REG2 ; No, skip this word
REG3
REG1
REG1, REG2 ; Yes, execute this word
REG3
LSB = 1
; is RAM location 0?
; Execute this word as a NOP
; continue code
; is RAM location 0?
; 2nd word of instruction
; continue code
EFh
C1h
0Fh
F0h
F4h
The CALL and GOTO instructions have the absolute pro-
gram memory address embedded into the instruction.
Since instructions are always stored on word boundar-
ies, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-4 shows how the
instruction GOTO
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 24.0 “Instruction Set Summary”
provides further details of the instruction set.
the instruction sequence. If the first word is skipped for
some reason and the second word is executed by itself,
a NOP is executed instead. This is necessary for cases
when the two-word instruction is preceded by a condi-
tional instruction that changes the PC. Example 5-4
shows how this works.
Note:
LSB = 0
55h
03h
00h
23h
56h
See Section 5.6 “PIC18 Instruction
Execution and the Extended Instruc-
tion Set” for information on two-word
instructions in the extended instruction set.
0006h is encoded in the program
Word Address
00000Ah
00000Ch
00000Eh
000000h
000002h
000004h
000006h
000008h
000010h
000012h
000014h
© 2008 Microchip Technology Inc.
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