PIC18F2520-I/ML Microchip Technology Inc., PIC18F2520-I/ML Datasheet - Page 50
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PIC18F2520-I/ML
Manufacturer Part Number
PIC18F2520-I/ML
Description
28 QFN 6x6mm TUBE, 32 KB Flash, 1536 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2520-IML.pdf
(412 pages)
Specifications of PIC18F2520-I/ML
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1K Bytes
Input Output
25
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Temperature Range
–40 to 125 °C
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2520-I/ML
Manufacturer:
MICROCHI
Quantity:
20 000
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PIC18F2420/2520/4420/4520
4.6
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
Reset situations, as indicated in Table 4-3. These bits
are used in software to determine the nature of the
Reset.
TABLE 4-3:
DS39631E-page 48
Power-on Reset
RESET Instruction
Brown-out Reset
MCLR Reset during Power-Managed
Run Modes
MCLR Reset during Power-Managed
Idle Modes and Sleep Mode
WDT Time-out during Full Power or
Power-Managed Run Mode
MCLR Reset during Full-Power
Execution
Stack Full Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
Stack Underflow Error (not an actual
Reset, STVREN = 0)
WDT Time-out during
Power-Managed Idle or Sleep Modes
Interrupt Exit from Power-Managed
Modes
Legend: u = unchanged
Note 1:
Reset State of Registers
When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
Condition
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
Program
PC + 2
Counter
PC + 2
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
(1)
RI
1
0
1
u
u
u
u
u
u
u
u
u
Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
TO
RCON Register
1
u
1
1
1
0
u
u
u
u
0
u
PD
1
u
1
u
0
u
u
u
u
u
0
0
POR
0
u
u
u
u
u
u
u
u
u
u
u
BOR
0
u
0
u
u
u
u
u
u
u
u
u
© 2008 Microchip Technology Inc.
STKFUL
STKPTR Register
0
u
u
u
u
u
u
1
u
u
u
u
STKUNF
0
u
u
u
u
u
u
u
1
1
u
u
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