PIC18F2520-I/ML Microchip Technology Inc., PIC18F2520-I/ML Datasheet - Page 136

• Manufacturer Part Number: PIC18F2520-I/ML
• Description: 28 QFN 6x6mm TUBE, 32 KB Flash, 1536 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2520-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 25
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Temperature Range: –40 to 125 °C
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F2420/2520/4420/4520
13.2
Timer2 also can generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1<1>). The interrupt is
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> (T2CON<6:3>).
FIGURE 13-1:
TABLE 13-1:
DS39631E-page 134
INTCON GIE/GIEH PEIE/GIEL
PIR1
PIE1
IPR1
TMR2
T2CON
PR2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1:
Name
T2OUTPS<3:0>
T2CKPS<1:0>
F
OSC
Timer2 Interrupt
/4
Timer2 Register
Timer2 Period Register
These bits are unimplemented on 28-pin devices; always maintain these bits clear.
PSPIE
PSPIP
PSPIF
Bit 7
—
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
(1)
(1)
(1)
TIMER2 BLOCK DIAGRAM
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Internal Data Bus
1:1, 1:4, 1:16
ADIE
ADIP
ADIF
Bit 6
2
Prescaler
TMR0IE
RCIF
RCIE
RCIP
Bit 5
4
TMR2
INT0IE
TXIE
TXIP
Bit 4
TXIF
Reset
8
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
13.3
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can optionally be used as the shift clock source
for the MSSP module operating in SPI mode. Addi-
tional information is provided in Section 17.0 “Master
Synchronous Serial Port (MSSP) Module”.
Comparator
1:1 to 1:16
Postscaler
8
TMR2/PR2
Match
Timer2 Output
TMR0IF
CCP1IF
CCP1IE
CCP1IP
Bit 2
TMR2IF
TMR2IE
TMR2IP
INT0IF
© 2008 Microchip Technology Inc.
Bit 1
PR2
8
Set TMR2IF
TMR2 Output
(to PWM or MSSP)
TMR1IF
TMR1IE
TMR1IP
RBIF
Bit 0
on page
Values
Reset
49
52
52
52
50
50
50