PIC18F2520-I/ML Microchip Technology Inc., PIC18F2520-I/ML Datasheet - Page 149

• Manufacturer Part Number: PIC18F2520-I/ML
• Description: 28 QFN 6x6mm TUBE, 32 KB Flash, 1536 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2520-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 25
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Temperature Range: –40 to 125 °C
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

16.0
In PIC18F4420/4520 devices, CCP1 is implemented as
a standard CCP module with Enhanced PWM
capabilities. These include the provision for 2 or 4 output
channels, user-selectable polarity, dead-band control
REGISTER 16-1:
© 2008 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3-0
Note:
R/W-0
P1M1
ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
The ECCP module is implemented only in
40/44-pin devices.
P1M<1:0>: Enhanced PWM Output Configuration bits
If CCP1M3:CCP1M2 = 00, 01, 10:
xx = P1A assigned as capture/compare input/output; P1B, P1C, P1D assigned as port pins
If CCP1M3:CCP1M2 = 11:
00 = Single output, P1A modulated; P1B, P1C, P1D assigned as port pins
01 = Full-bridge output forward, P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output, P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins
11 = Full-bridge output reverse, P1B modulated; P1C active; P1A, P1D inactive
DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in
CCPR1L.
CCP1M<3:0>: Enhanced CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Reserved
0010 = Compare mode, toggle output on match
0011 = Capture mode
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, initialize CCP1 pin low; set output on compare match (set CCP1IF)
1001 = Compare mode, initialize CCP1 pin high; clear output on compare match (set CCP1IF)
1010 = Compare mode, generate software interrupt only; CCP1 pin reverts to I/O state
1011 = Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CCP1IF bit)
1100 = PWM mode, P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode, P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode, P1A, P1C active-low; P1B, P1D active-high
1111 = PWM mode, P1A, P1C active-low; P1B, P1D active-low
R/W-0
P1M0
CCP1CON: ECCP CONTROL REGISTER (40/44-PIN DEVICES)
W = Writable bit
‘1’ = Bit is set
DC1B1
R/W-0
PIC18F2420/2520/4420/4520
DC1B0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CCP1M3
R/W-0
and automatic shutdown and restart. The enhanced
features are discussed in detail in Section 16.4
“Enhanced PWM Mode”. Capture, Compare and
single output PWM functions of the ECCP module are
the same as described for the standard CCP module.
The control register for the Enhanced CCP module is
shown in Register 16-2. It differs from the CCPxCON
registers in PIC18F2420/2520 devices in that the two
Most Significant bits are implemented to control PWM
functionality.
CCP1M2
R/W-0
x = Bit is unknown
CCP1M1
R/W-0
DS39631E-page 147
CCP1M0
R/W-0
bit 0