DP83850CVF National Semiconductor, DP83850CVF Datasheet - Page 18

• Manufacturer Part Number: DP83850CVF
• Description: IC CONTROLLER INTERFACE 132-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83850CVF

• Controller Type: Ethernet Repeater Interface Controller
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 295mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83850CVF

4.0 Registers
4.4 Page Register (PAGE)
4.5 Partition Status Register (PARTITION)
4.6 Jabber Status Register (JABBER)
Page 0
Page 1
D15 - D2 reserved
D1 - D0 PAGE[1:0]
Page 0
D15 - D12 reserved
D11 - D0
Page 0
D15 - D12 reserved
D11 - D0
Bit
Bit
D1
D0
Bit
Bit
PHY_ACCESS
Bit Name
PART[11] ...
PART[0]
JAB[11..0] read only The respective port's JAB bit is set to 1 when the Jabber condition is detected on that
Bit Name Access
RST_RSM
Bit Name
Bit Name
Address 1h
Address 1h
Address 2h
Address 3h
(Continued)
cess
-
Ac-
r/w
-
-
read only The respective port's PART bit is set to 1 when Partitioning is sensed on that port.
Access
Access
r/w
r/w
These bits are undefined when read. Must be written as 0.
These bits program the register page to be accessed. The page encoding is as follows:
PAGE[1:0]
These bits are undefined when read.
port. After reset, these bits are cleared to zero.
0h
1h
2h
3h
This bit allows the management agent to access the DP83840A PHY chip’s register
via the MII serial protocol.
0:
1:
Note: When in PHY_access mode, RDIO will be driven by the DP83850C during the
read phase for all read commands. This is to allow the DP83840A Physical Layer de-
vices to pass their data through their local DP83850C. While in this mode, contention
will result (on the RDIO line) if any device other than this DP83850C or the DP83840A
Physical Layer devices are accessed.
Setting this bit holds the Repeater State Machines in reset. The management event
flags and counters are unaffected by this bit. Setting this bit while a reception is in
progress may truncate the packet.
0:
1:
These bits are undefined when read.
After reset, these bits are cleared to zero.
PHY access disabled (default).
PHY register access enabled.
DP83850C in normal operation (default).
DP83850C held in reset.
reserved
reserved
Page
0
1
(default)
18
Bit Description
Bit Description
Bit Description
Bit Description
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