DP83850CVF National Semiconductor, DP83850CVF Datasheet
DP83850CVF
Specifications of DP83850CVF
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DP83850CVF Summary of contents
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... Note: The above system diagram depicts the repeater configured in 100BASE-TX mode. ® FAST is a registered trademark of Fairchild Semiconductor Corporation. ® TRI-STATE is a registered trademark of National Semiconductor Corporation. ™ 100RIC is a trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation Features IEEE 802 ...
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Block Diagram MANAGEMENT & INTER REPEATER BUS INTERFACE EE_CK EE_CS EE_DI EE_DO RDIR RDIO RDC /SDV GRDIO BRDC PART[5:0] Active Port # ACTIVITY[11:0] RXD[3:0], RX_ER, RXC, RX_DV TXD[3:0], TX_ER TXE[11:0] RXE[11:0] CRS[11:0] PHYSICAL LAYER INTERFACE 2 www.national.com ...
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Pin Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Pin Table . . . . . . . . ...
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... RXE3 45 GND 46 VCC 47 RXE4 48 RXE5 49 RXE6 50 100 Mb/s TX/T4 Repeater Interface Controller (100RIC) 132 pin PQFP (top view) Order Number DP83850CVF NS Package Number VF132A 4 116 /M_DV 115 M_CK /M_ER 114 113 /IR_BUS_EN 112 VCC 111 GND 110 /ACTIVE0 109 /SDV 108 ...
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Pin Connection Diagram 1.1 Pin Table Pin Name /ACTIVEO /IR_ACTIVE /IR_BUS_EN /IR_COL_IN /IR_COL_OUT /IRD_ER /IRD_V /M_DV /M_ER /RST /SDV BRDC CRS[11:0] EE_CK EE_CS EE_DI EE_DO GND 1, 8, 16, 28, 46, 56, 66,76, 85, 94, 101, 111, 117,123 GRDIO ...
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Pin Descriptions 2.1 Physical Layer Interface Signal Name Type Active RXD[3:0] I — Receive Data: Nibble data inputs from each Physical layer chip ports are sup- ported. Note: Input buffer has a weak pull-up. RXE[11:0] O, ...
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Pin Descriptions (Continued) 2.2 Inter Repeater and Management Bus Interface Signal Name Type Active IRD[3:0] I/O/Z, M — Inter Repeater Data: Nibble data input/output. Transfers data from the “active” DP83850C to all other “inactive” DP83850Cs. The bus master of ...
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Pin Descriptions (Continued) Signal Name Type Active /IR_BUS_EN O,L low Inter-Repeater Bus Enable: This signal is asserted at all times (either when the 100RIC is driving the bus or receiving from the bus) and it is deasserted only when ...
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Pin Descriptions (Continued) Signal Name Type Active PART[5: — Partition: Used to indicate each port's Jabber and Partition status. PART[3:0] cycle through each port number (0-11) continuously. PART[4] indicates the Partition status for each port (1 = ...
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Functional Description The following sections describe the different functional blocks of the DP83850C 100 Mb/s Repeater Interface Con- troller. The IEEE 802.3u repeater specification details a number of functions a repeater system is required to per- form. These functions ...
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Functional Description 3.6 Jabber Protection State Machine The jabber specification for 100BASE-T is functionally dif- ferent than 10BASE-T. In 10BASE-T, each port's Jabber Protect State machine ensures that Jabber transmissions are stopped after 5ms and followed ...
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Functional Description Activity on the 100RIC with RID=00010 Activity on the 100RIC with RID=00011 /IR_Vect value on the backplane Activity on the 100RIC with RID=00011 Activity on the 100RIC with RID=00010 /IR_VECT value on the backplane 3.9 Management Bus ...
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Functional Description Subsequently writing 0000h to the PAGE register in Regis- ter Page 1 switches the registers back to Register Page 0. All accesses to DP83850C registers and counters, and to the connected Physical Layer devices (via the DP83850C), ...
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Functional Description Management CPU Bus Figure 3. Serial Management Addressing Scheme (Continued) phy_access = 0 ≈ ≈ phy_access = 1 phy_access = 0 14 ≈ ≈ ≈ ≈ ≈ ≈ www.national.com ...
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Functional Description This preamble only needs to be sent once (at reset). From then on, the <start> field lets the receive logic know where the beginning of the data frame occurs. To access the Physical Layer devices via the ...
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Registers The DP83850C has 64 registers in 2 pages of 32 16-bit registers. At power-on and/or reset, the DP83850C defaults to Page 0 registers. The register page can be changed by writing to the PAGE register in either register ...
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Registers (Continued) 4.2 Page 1 Register Map Address Name Access (hex) 0 CONFIG r/w Sets the DP83850C configuration (same as page 0 CONFIG register). 1 PAGE r/w Select either register page Reserved 3 ...
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Registers (Continued) Bit Bit Name Access D1 PHY_ACCESS r/w This bit allows the management agent to access the DP83840A PHY chip’s register via the MII serial protocol Note: When in PHY_access mode, RDIO will be driven by ...
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Registers (Continued) 4.7 Administration Register (ADMIN) Page 0 Address 4h Bit Bit Name Access D15 - D13 reserved - D12 TST_PART_LED r/w D11 - D0 ADMIN_DIS[11] ... r/w ADMIN_DIS[0] 4.8 Device ID Register (DEVICEID) Page 0 Address 5h Bit ...
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Registers (Continued) 4.10 Hub ID 1 Register (HUBID1) Page 0 Address 7h Bit Bit Name Access D15 - D0 HUB_ID1[15:0] r/w Hub ID 1: Contains the second 16 bits read from the EEPROM. The first bit read will be ...
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... An example of this is shown in Figure 7. tion Note and/or their National Semiconductor representa- tive prior to attempting a design. Further system timing analysis shows that the RXD[3:0], RX_DV and RX_ER sig- nals should be latched into the DP83850C from the con- nected DP83840s ...
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DP83850C Applications is the BTL logic transceiver family: this approach has the advantage of significantly lower noise and may assist in successful passing of FCC and other EMI tests. Figure 8 shows the signal connections on the Inter-RIC bus. ...
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... F32 ABT125 F32 ABT125 Figure 8. Inter Repeater Bus Connections 23 ABT125 IR_VECT4_BP IR_VECT3_BP ABT125 IR_VECT2_BP ABT125 IR_VECT1_BP ABT125 IR_VECT0_BP /IR_ACTIVE_BP Note 1 - The Inter Repeater Bus must be terminated at both ends. Note 2 - All logic, bus drivers and transceivers are available from National Semiconductor. www.national.com ...
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DP83850C Applications DP83850C 100RIC 74F27 /ACTIVEO IRD_ODIR IRD3 IRD2 IRD1 IRD0 IRD_CK P /IRD_V /IRD_ER MD3 MD2 MD1 MD0 MD_CK P /MD_V /MD_ER P = Pull-Ups, 1.2k ohms (Continued) 74ABT16245C /OE DIR ...
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DP83850C Applications 5.4 DP83856 100RIB Connections To achieve a practical managed 100Mb/s repeater design that keeps up with the fast flow of network information, a hardware statistics gathering engine is required. The DP83856 100Mb/s Repeater Information Base device (100RIB) ...
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DP83850C Applications 5.5 Port Partition and Jabber Status LEDs Port Partition and Jabber Status must be decoded from the PART[5:0] outputs as described in section 3.11. One possi- ble decoder implementation is shown in Figure 11. This uses 74LS259 ...
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A.C. and D.C. Specifications Absolute Maximum Rating and Recommended Operating Conditions Supply Voltage (Vdd) Supply voltage (Vdd) DC Input Voltage (Vin) -0 Vcc + 0.5 V Ambient Temperature (Ta) DC Output Voltage (Vout) -0 Vcc ...
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A.C. and D.C. Specifications 6.2 A.C. Specifications 6.2.1 Receive Timing T0 CRSx to RXEx assertion delay (Note 1) T1 CRSx to RXEx de-assertion delay with no collision T2 CRSx to RX_DV delay requirement (Note 2) T3 /IRD_V setup to ...
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A.C. and D.C. Specifications 6.2.2 Transmit, Partition and RID_ER Timing T7 TX_RDY delay from LCK high T8 TXE[11:0] delay from LCK high T9 TXD[3:0] or TX_ER valid time from LCK high T10 PART[5:0] valid time from LCK high T11 ...
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A.C. and D.C. Specifications 6.2.3 Inter Repeater Receive and Intra-Repeater Collision Timing T12 Receive to Inter Repeater Bus delay T12a Receive to Inter Repeater Bus skew T13 CRSx assertion (de-assertion) to -ACTIVEO assertion (de-assertion) T14 CRSx assertion (de-assertion) to ...
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A.C. and D.C. Specifications 6.2.4 Inter Repeater Collision Timing T19 IR_VECT[4:0] change to /IR_COL_OUT assertion[de-assertion] T20 /IR_COL_OUT assertion to IRD_ODIR de-assertion T20A /ACTIVEO low to IR_VECT[4:0] feedback Note 9: This timing refers to the condition where the repeater has ...
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A.C. and D.C. Specifications 6.2.6 Management Bus - Input Mode Timing T24 /M_DV setup to M_CK high T25 /M_DV hold from M_CK high T26 MD[3:0] or /M_ER setup to M_CK high T27 MD[3:0] or /M_ER hold from M_CK high ...
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A.C. and D.C. Specifications 6.2.7 Serial Register Write Timing T28 RDC period T29 12 RDC high time T30 12 RDC low time T31 RDC to BRDC delay T32 RDIO setup to RDC high T33 RDIO hold from RDC high ...
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A.C. and D.C. Specifications 6.2.8 Serial Register Read Timing T37 RDIO valid from RDC T38 14 GRDIO to RDIO delay Note 14:Serial data will be gated from GRDIO to RDIO during read operations when the “phy_access” bit in the ...
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A.C. and D.C. Specifications 6.2.9 EEPROM Access Timing T39 EE_SK period 15 T40 EE_SK high time 15 T41 EE_SK low time 15 T42 EE_CS assertion [de-assertion] from EE_SK low T43 EE_DI assertion [de-assertion] from EE_SK low T44 EE_DO setup ...
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A.C. and D.C. Specifications 6.2.10 Clocks, Reset and RID Timing T46 LCK period T47 LCK high time T48 LCK low time T48a LCK frequency tolerance 16 T49 /RST assertion time T50 RID[4:0] setup to LCK high T51 M_CK period ...
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... National Semiconductor National Semiconductor Europe Asia Pacific Customer Response Group Fax: (+49) 0-180-530 85 86 Tel: 65-254-4466 Email: europe.support@nsc.com Deutsch Tel: (+49) 0-180-530 85 85 Fax: 65-250-4466 English Tel: (+49) 0-180-532 78 32 Email: sea.support@nsc.com VF132A (REV D) National Semiconductor Japan Ltd. Tel: 81-043-299-2308 Fax: 81-043-299-2408 ...