DP83850CVF National Semiconductor, DP83850CVF Datasheet - Page 15

• Manufacturer Part Number: DP83850CVF
• Description: IC CONTROLLER INTERFACE 132-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83850CVF

• Controller Type: Ethernet Repeater Interface Controller
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 295mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83850CVF

3.0 Functional Description
This preamble only needs to be sent once (at reset). From
then on, the <start> field lets the receive logic know where
the beginning of the data frame occurs.
To access the Physical Layer devices via the serial bus, the
DP83850C has a “phy_access” mode. When in this mode,
the register data input/output (RDIO) is gated to the
GRDIO pin. This signal is connected to the serial data pins
of the Physical Layer devices.
In this mode the buffers which drive RDIO and GRDIO will
turn on in the appropriate direction for each serial access.
In order to avoid possible contention problems, the user
must ensure that only one DP83850C at a time has the
"phy_access" bit set. The CONFIG register contains the
“phy_access” bit, which can be set or cleared at any time.
Figure 3 shows a possible system implementation of the
RDIO/GRDIO connection scheme. In this example, the
DP83850C with address 00001 has its "phy_access" bit
set, allowing its twelve DP83840 PHY devices to be
accessed by the DP83856 100RIB.
3.13 EEPROM Serial Read Access
After reset is de-asserted, the DP83850C will serially read
an NM93C06 EEPROM (or equivalent). Only the first 32-
bits starting from address 0 will be read. Write access is
not provided. The data is written to registers HUBID0 and
HUBID1. The first bit read is written to HUBID0[0]; the last
bit read will be written to HUBID1[15].
The DP83850C EEPROM interface implements the serial
protocol as shown in Figure 3. The DP83850C will issue
two read commands to obtain the 32-bit ID. The serial
clock, EE_CK will be continuous. For more explicit timing
diagrams please refer to the NM93C06 datasheet.
EE_CS
EE_DI
EE_DO
<device addr> 00000 - 11111 Five bits are provided to address up to 32 devices.
<reg addr>
<opcode>
<start>
Field
<1...10><00000><1...>
00000 - 11111 Five bits are provided to address up to 32 16-bit registers.
Encoding
all others
Table 1. Serial Register Interface Encoding
01
10
01
(Continued)
Figure 4. Serial EEPROM Access Protocol
Indicates the beginning of an opcode operation.
Read
Write
Reserved
<0><D15..D0>
15
MII serial management contention problems can be
avoided by keeping to the addressing convention shown in
Figure 3.
3.12 Jabber/Partition LED Driver Logic
This logic encodes the current auto-partition status (from
the PARTITION register) and the jabber status (from the
JABBER register), and outputs this information to
PART[5:0] pins. PART[3:0] cycles through each port num-
ber and PART[5:4] indicates the port’s status. PART[5]
indicates the Jabber status for each port (0 = LED OFF, 1
=LED ON - Port Jabbering). PART[4] indicates the Partition
status for each port (0 = LED OFF, 1 = LED ON - Port Auto-
Partitioned).
The port number on PART[3:0] is cycled with a 25MHz.
External logic is required to decode the PART[5:0] outputs
and drive the Partition and Jabber LEDs. Multi-color LEDs
could be driven with the appropriate logic if required.
One possible implementation of a DP83850C Port Partition
and Jabber Status LED scheme is given in section 5.5.
The NM93C06 EEPROM must be pre-programmed with
the HUBID value prior to fitting the device to the circuit
since the DP83850C does not support programming of this
device in circuit.
Description
<1...0><00001><1...>
<0><D31..D16>
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