DP83850CVF National Semiconductor, DP83850CVF Datasheet - Page 17

• Manufacturer Part Number: DP83850CVF
• Description: IC CONTROLLER INTERFACE 132-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83850CVF

• Controller Type: Ethernet Repeater Interface Controller
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 295mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83850CVF

4.0 Registers
4.2 Page 1 Register Map
4.3 Configuration Register (CONFIG)
Page 0
Page 1
D15 - D6
Address
1C - 1F P11_SE ...
18 - 1B P10_SE ...
10 - 13
14 - 17
(hex)
8 - B
C - F
5 - 7
Bit
D5
D4
D3
D2
0
1
2
3
4
COL_LIMIT32
CONFIG
PAGE
-
-
SIREV
-
P6_SE ...
P6_PART
P7_SE ...
P7_PART
P8_SE ...
P8_PART
P9_SE ...
P9_PART
P10_PART
P11_PART
REGEN_PRE
DIS_PART
Bit Name
reserved
Name
MGTEN
Address 0h
Address 0h
(Continued)
read only Silicon revision code.
Access
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
-
-
-
r/w
r/w
r/w
r/w
-
Sets the DP83850C configuration (same as page 0 CONFIG register).
Select either register page 0 or 1.
Reserved
Reserved
Reserved
Port 6 management counters (as per ports 0, 1 above).
Port 7 management counters (as per ports 0, 1 above).
Port 8 management counters (as per ports 0, 1 above).
Port 9 management counters (as per ports 0, 1 above).
Port 10 management counters (as per ports 0, 1 above).
Port 11 management counters (as per ports 0,1 above).
For compatibility with future enhanced versions these bits must be written as zero.
They are undefined when read.
Regenerate Preamble: This bit may be used to overwrite/change the repeater mode
(TX or T4) that is set by the MODE[1:0] pins at power-up. If MODE[1:0] is 1, 1 then
this bit is set, otherwise this bit will be zero.
The time when the preamble is regenerated depends upon the type of the PHY (ei-
ther TX or T4 PHYs) attached to the repeater. For a TX PHY, preamble is regenerat-
ed approximately 4 clocks (RXC) after the /IR_ACTIVE assertion, and for a T4 PHY,
preamble is regenerated approximately 12 clocks after the /IR_ACTIVE assertion.
Management Enable: This bit enables all the management counters.
0:
1:
Note: The management counters can only be reliably written to when they are dis-
abled.
This bit configures the collision limit for Auto-Partitioning algorithm:
0:
1:
This bit disables the Auto-Partitioning algorithm:
0:
1:
Management Counters disabled (default).
Management Counters enabled.
Consecutive Collision Limit set to 64 consecutive collisions (default). A port will
be partitioned on the 65th consecutive collision.
Consecutive Collision Limit set to 32 consecutive collisions. A port will be parti-
tioned on the 33rd consecutive collision.
Auto-Partitioning is not disabled (default).
Auto-Partitioning is disabled.
17
Bit Description
Description
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