ENC28J60-I/SO Microchip Technology, ENC28J60-I/SO Datasheet - Page 66

• Manufacturer Part Number: ENC28J60-I/SO
• Description: IC ETHERNET CTRLR W/SPI 28SOIC
• Manufacturer: Microchip Technology

Specifications of ENC28J60-I/SO

• Package / Case: 28-SOIC (7.5mm Width)
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.1 V to 3.6 V
• Supply Current (max): 180 mA
• Data Rate: 10Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: SPI
• Supply Current: 180mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Ethernet Connection Type: 10Base-T
• Digital Ic Case Style: SOIC
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC28J60
12.1
The INT Interrupt Enable bit (INTIE) is a global enable
bit which allows the following interrupts to drive the INT
pin:
• Receive Error Interrupt (RXERIF)
• Transmit Error Interrupt (TXERIF)
• Transmit Interrupt (TXIF)
• Link Change Interrupt (LINKIF)
• DMA Interrupt (DMAIF)
• Receive Packet Pending Interrupt (PKTIF)
REGISTER 12-1:
DS39662C-page 64
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R-0
INT
INT Interrupt Enable (INTIE)
CLKRDY resets to ‘0’ on Power-on Reset but is unaffected on all other Resets.
INT: INT Interrupt Flag bit
1 = INT interrupt is pending
0 = No INT interrupt is pending
BUFER: Ethernet Buffer Error Status bit
1 = An Ethernet read or write has generated a buffer error (overrun or underrun)
0 = No buffer error has occurred
Reserved: Read as ‘0’
LATECOL: Late Collision Error bit
1 = A collision occurred after 64 bytes had been transmitted
0 = No collisions after 64 bytes have occurred
Unimplemented: Read as ‘0’
RXBUSY: Receive Busy bit
1 = Receive logic is receiving a data packet
0 = Receive logic is Idle
TXABRT: Transmit Abort Error bit
1 = The transmit request was aborted
0 = No transmit abort error
CLKRDY: Clock Ready bit
1 = OST has expired; PHY is ready
0 = OST is still counting; PHY is not ready
BUFER
R/C-0
ESTAT: ETHERNET STATUS REGISTER
C = Clearable bit
‘1’ = Bit is set
R-0
r
(1)
LATECOL
R/C-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
When any of the above interrupts are enabled and
generated, the virtual bit, INT in the ESTAT register
(Register 12-1), will be set to ‘1’. If EIE.INTIE is ‘1’, the
INT pin will be driven low.
12.1.1
The registers associated with the INT interrupts are
shown in Register 12-2, Register 12-3, Register 12-4
and Register 12-5.
U-0
—
INT INTERRUPT REGISTERS
RXBUSY
R-0
© 2008 Microchip Technology Inc.
x = Bit is unknown
TXABRT
R/C-0
CLKRDY
R/W-0
bit 0
(1)