COM20019I-DZD SMSC, COM20019I-DZD Datasheet - Page 54

• Manufacturer Part Number: COM20019I-DZD
• Description: IC CTRLR ARCNET 2KX8 RAM 28-PLCC
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20019I-DZD

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 20mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1000-5

Rev. 09-25-07
Figure 8.7 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE
D0-D7
A0-A2
nCS
nDS
DIR
**
Note 1:
Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access
*
T
T
T
T
t10
t11
ARB
ARB
ARB
opr
t1
t3
t4
t6
t2
t5
t7
t8
t9
now be 45nS measured from the leading edge of nCS.
nCS may become active after control becomes active, but the access time (t8) will
is the period of operation clock. Same as the XTAL1 period.
is the Arbitration Clock Period
is identical to T
is twice T
The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
to Data Register requires a minimum of 5T
the leading edge of the next nDS.
Address Setup to nDS Active
nCS Setup to nDS Active
nCS Hold from nDS Inactive
Address Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS Low to Next Time Low)
DIR Hold from nDS Inactive
nDS Low to Valid Data
nDS High to Data High Impedence
nDS Low Width
nDS High Width
opr
if SLOW ARB = 1
t1
opr
if SLOW ARB = 0
DATASHEET
t5
t3
Parameter
CASE 1: RBUSTMG bit = 0
Page 54
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
t8
VALID
ARB
from the trailing edge of nDS to
t10
t6
VALID DATA
4T
min
15
10
10
10
5**
60
20
ARB
0
0
*
max
40**
20
t9
t7
t2
t4
Note 2
t11
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
SMSC COM20019I