COM20019I-DZD SMSC, COM20019I-DZD Datasheet - Page 29

• Manufacturer Part Number: COM20019I-DZD
• Description: IC CTRLR ARCNET 2KX8 RAM 28-PLCC
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20019I-DZD

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 20mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1000-5

SMSC COM20019I
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
2
1
1,0
0000 0000
0000 0001
0000 0010
b0fn n100
00fn n011
BIT
DATA
Tentative ID
New Next ID
(Reserved)
BIT NAME
Clear
Transmit
Interrupt
Disable
Transmitter
Disable
Receiver
Enable
Receive to
Page fnn
Enable
Transmit from
Page fnn
COMMAND
SYMBOL
TENTID
NEW
NXTID
Table 6.5 - Command Register
This bit, if high, indicates that a response to a token whose DID
matches the value in the Tentative ID Register has occurred.
The second DID and the trailing zero's are not checked. Since
each node sees every token passed around the network, this
feature can be used with the device on-line in order to build and
update a network map. Refer to the Improved Diagnostics
section for further detail.
This bit, if high, indicates that the Next ID Register has been
updated and that a node has either joined or left the network.
Reading the Diagnostic Status Register does not clear this bit.
This bit, when set, will cause an interrupt if the corresponding bit
in the IMR is also set. The bit is cleared by reading the Next ID
Register.
These bits are undefined.
DATASHEET
This command is used only in the Command Chaining
operation. Please refer to the Command Chaining section for
definition of this command.
This command will cancel any pending transmit command
(transmission that has not yet started) and will set the TA
(Transmitter Available) status bit to logic "1" when the
COM20019I next receives the token.
This command will cancel any pending receive command. If the
COM20019I is not yet receiving a packet, the RI (Receiver
Inhibited) bit will be set to logic "1" the next time the token is
received. If packet reception is already underway, reception will
run to its normal conclusion.
This command allows the COM20019I to receive data packets
into RAM buffer page fnn and resets the RI status bit to logic
"0". The values placed in the "nn" bits indicate the page that the
data will be received into (page 0, 1, 2, or 3). If the value of "f"
is a logic "1", an offset of 256 bytes will be added to that page
specified in "nn", allowing a finer resolution of the buffer. Refer
to the Selecting RAM Page Size section for further detail. If the
value of "b" is logic "1", the device will also receive broadcasts
(transmissions to ID zero). The RI status bit is set to logic "1"
upon successful reception of a message.
This command prepares the COM20019I to begin a transmit
sequence from RAM buffer page fnn the next time it receives
the token. The values of the "nn" bits indicate which page to
transmit from (0, 1, 2, or 3). If "f" is logic "1", an offset of 256
bytes is the start of the page specified in "nn", allowing a finer
resolution of the buffer. Refer to the Selecting RAM Page Size
section for further detail. When this command is loaded, the TA
and TMA bits are reset to logic "0". The TA bit is set to logic "1"
upon completion of the transmit sequence. The TMA bit will
have been set by this time if the device has received an ACK
from the destination node. The ACK is strictly hardware level,
sent by the receiving node before its microcontroller is even
aware of message reception. Refer to Figure 1 for details of the
transmit sequence and its relation to the TA and TMA status
bits.
Page 29
DESCRIPTION
DESCRIPTION
Rev. 09-25-07