COM20019I-DZD SMSC, COM20019I-DZD Datasheet - Page 50

• Manufacturer Part Number: COM20019I-DZD
• Description: IC CTRLR ARCNET 2KX8 RAM 28-PLCC
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20019I-DZD

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 20mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1000-5

Rev. 09-25-07
Figure 8.3 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE
AD0-AD2,
D3-D7
**
nCS
ALE
nDS
DIR
Note 1:
Note 2:
*
T
T
T
T
t10
t11
t12
t13
t14
ARB
ARB
ARB
opr
t1
t2
t3
t4
t5
t6
t7
t8
t9
is the period of operation clock. Same as the XTAL1 period.
is the Arbitration Clock Period
is identical to T
is twice T
Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4T
next nDS.
Write cycle for Address Pointer Low Register occurring after an access to
Data Register requires a minimum of 5T
the leading edge of the next nDS.
Address Setup to ALE Low
The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
Valid Data Setup to nDS High
Data Hold from nDS High
Cycle Time (nDS
DIR Setup to nDS Active
DIR Hold from nDS Inactive
ALE High Width
ALE Low Width
nDS Low Width
nDS High Width
opr
if SLOW ARB = 1
t11
t1
opr
VALID
t3
if SLOW ARB = 0
ARB
from the trailing edge of nDS to the leading edge of the
Parameter
DATASHEET
to Next
t2,
t4
t5
t9
)**
Page 50
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
ARB
from the trailing edge of nDS to
t12
VALID DATA
t13
t6
4T
min
10
10
20
20
20
20
30
10
20
10
10
10
15
ARB
*
max
t7
t10
t14
Note 2
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
t8**
t8
SMSC COM20019I