COM20019I-DZD SMSC, COM20019I-DZD Datasheet - Page 4

• Manufacturer Part Number: COM20019I-DZD
• Description: IC CTRLR ARCNET 2KX8 RAM 28-PLCC
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20019I-DZD

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 20mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1000-5

Chapter 7
Chapter 8
Chapter 9
Chapter 10
Chapter 11
LIST OF FIGURES
Figure 3.1 - COM20019I OPERATION ........................................................................................................................10
Figure 5.1 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE ............................................16
Figure 5.2 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE...................................17
Figure 5.3 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE............................................................................18
Figure 5.4 - COM20019I NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS...........................................20
Figure 5.5 - INTERNAL BLOCK DIAGRAM ..................................................................................................................21
Figure 6.1 - SEQUENTIAL ACCESS OPERATION ......................................................................................................35
Figure 6.2 - RAM BUFFER PACKET CONFIGURATION .............................................................................................37
Figure 6.3 - COMMAND CHAINING STATUS REGISTER QUEUE..............................................................................39
Figure 7.1 - AC MEASUREMENTS ..............................................................................................................................47
Figure 8.1 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE .................................................48
Figure 8.2 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE .................................................49
Figure 8.3 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE................................................50
Figure 8.4 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE................................................51
Figure 8.5 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................52
Figure 8.6 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................53
Figure 8.7 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................54
Figure 8.8 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................55
Figure 8.9 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE ......................................56
Figure 8.10 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE ....................................57
Figure 8.11 - BACKPLANE MODE TRANSMIT OR RECEIVE TIMING.......................................................................58
Figure 8.12 - TTL INPUT TIMING ON XTAL1 PIN .......................................................................................................59
Figure 8.13 - RESET AND INTERRUPT TIMING ........................................................................................................59
Figure 10.1 - EFFECT OF THE EB BIT ON THE TA/RI BIT ........................................................................................63
Figure 11.1 - EXAMPLE OF INTERFACE CIRCUIT DIAGRAM TO ISA BUS .............................................................65
LIST OF TABLES
Table 5.1 - Typical Media .............................................................................................................................................22
Table 6.1 - Read Register Summary.............................................................................................................................23
Table 6.2 - Write Register Summary ............................................................................................................................24
Table 6.3 - Status Register ...........................................................................................................................................27
Table 6.4 - Diagnostic Status Register..........................................................................................................................28
Table 6.5 - Command Register.....................................................................................................................................29
Table 6.6 - Address Pointer High Register ....................................................................................................................30
Table 6.7 - Address Pointer Low Register.....................................................................................................................30
Table 6.8 - Sub Address Register .................................................................................................................................31
Table 6.9 - Configuration Register ................................................................................................................................31
Table 6.10 - Setup 1 Register .......................................................................................................................................32
Table 6.11 - Setup 2 Register .......................................................................................................................................33
Rev. 09-25-07
6.9
7.1
7.2
9.1
9.2
10.1
10.2
6.8.2
OSCILLATOR ............................................................................................................................................43
MAXIMUM GUARANTEED RATINGS*......................................................................................................45
DC ELECTRICAL CHARACTERISTICS ....................................................................................................45
28 Pin PLCC Package Outline and Parameters.........................................................................................60
48 Pin TQFP Package Outline and Parameters.........................................................................................61
NOSYNC Bit ...........................................................................................................................................62
EF Bit......................................................................................................................................................62
Abnormal Results:...............................................................................................................................43
OPERATIONAL DESCRIPTION .......................................................................................... 45
TIMING DIAGRAMS............................................................................................................. 48
Package Outlines ................................................................................................................. 60
APPENDIX A........................................................................................................................ 62
APPENDIX B:....................................................................................................................... 65
DATASHEET
Page 4
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20019I