AD1843JS Analog Devices Inc, AD1843JS Datasheet - Page 5

• Manufacturer Part Number: AD1843JS
• Description: IC CODEC STEREO 5V 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1843JS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 92 / 86
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 80
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 2.85 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP

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ANALOG OUTPUT
LOUT1 Full-Scale Output Voltage
LOUT2 Full-Scale Single-Ended Output Voltage
LOUT2 Full-Scale Differential Output Voltage
LOUT1 Output Impedance*
LOUT2 Output Impedance*
LOUT1 External Load Impedance*
LOUT2 External Load Impedance*
MOUT External Load Impedance*
HPOUT External Load Impedance*
HPOUT THD+N (Referenced to Full Scale, 32
Output Capacitance*
External Load Capacitance*
CMOUT
External CMOUT Load Current*
CMOUT Output Impedance*
Mute Click* (Muted Output Minus Unmuted Midscale DAC1 and DAC2 Outputs)
SYSTEM SPECIFICATIONS
System Frequency Response Ripple* (Line-In to Line-Out)
Differential Nonlinearity*
Phase Linearity Deviation*
STATIC DIGITAL SPECIFICATIONS
High-Level Input Voltage (V
Low-Level Input Voltage (V
High-Level Output Voltage (V
Low-Level Output Voltage (V
Input Leakage Current (GO/NOGO Tested)
Output Leakage Current (GO/NOGO Tested)
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE AND DIGITAL SUPPLY RANGE)
Serial Data Frame Sync [SDFS] Period (t
Frame Sync [SDFS] HI Pulse Width (t
Clock [SCLK] to Frame Sync [SDFS] Propagation Delay (t
Data [SDI] Input Setup Time to SCLK (t
Data [SDI] Input Hold Time from SCLK (t
Clock [SCLK] to Output Data [SDO] Valid (t
Clock [SCLK] to Output Data [SDO] Three-State [High-Z] (t
Clock [SCLK] to Time Slot Output [TSO] Propagation Delay (t
RESET and PWRDWN LO Pulse Width (t
SCLK
SDFS
SDO
SDI
(RMS Values Assume Sine Wave Input)
(RMS Values Assume Sine Wave Input)
(RMS Values Assume Sine Wave Input)
Digital Inputs, Except SCLK
XTALI and SCLK
(Master Mode, FRS = 1 [16 Slots per Frame], SCF = 0 [SCLK = 12.288 MHz])
t
PD1
t
2
t
S
BIT 15
BIT 15
t
H
IL
IH
)
OL
OH
BIT 14
)
t
BIT 14
DV
)
)
2
)
1
S
)
)
RPWL
H
)
DV
)
)
External Load Impedance)
BIT 0
BIT 0
Figure 1. Timing Diagrams
t
HZ
PD1
HZ
)
PD2
SDI OR SDO
)
PWRDWN
)
–5–
RESET
SCLK
SDFS
TSO
15 14 13
t
PD1
Min
1.8
1.8
3.6
10
2
10
16
2.10
Min
10
10
100
t
RPWL
Typ
0.707
2.0
0.707
2.0
1.414
4.0
32
0.10
–60
2.25
4
Min
2.0
2.4
–0.3
2.4
–10
–10
Typ
20.833
80
TIME SLOT
t
VALID
1
LAST
3 2 1 0 15 14 13
2.2
2.2
4.4
V
Max
600
1
15
100
2.40
10
Max
1.0
5
Max
V
0.8
0.4
10
10
Max
15
15
15
15
t
5
1
DD
DD
PD2
+ 0.3
+ 0.3
AD1843
Units
V rms
V p-p
V rms
V p-p
V rms
V p-p
k
k
k
%
dB
pF
pF
V
k
mV
Units
dB
Bit
Degrees
Units
V
V
V
V
V
Units
ns
ns
ns
ns
ns
ns
ns
ns
A
A
A
s
15 1413