AD1843JS Analog Devices Inc, AD1843JS Datasheet - Page 38

• Manufacturer Part Number: AD1843JS
• Description: IC CODEC STEREO 5V 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1843JS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 92 / 86
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 80
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 2.85 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP

AD1843
C1VID
C1PLLG
C1P200
C1X8/7
C1C128
res
C1M7:0
Clock Generator 1 Video Lock Mode. This bit is used to select between lock modes when the Clock Generator 1 is
Clock Generator 1 PLL Loop Gain Select. If reset to “0,” this bit selects finite PLL loop gain, and if set to “1,” this
Clock Generator 1 Bit Clock +200 Frequency Modifier. When set to “1,” the Bit clock driven out of pin BIT1 will
Clock Generator 1 Conversion Clock 8/7 Frequency Modifier. When set to “1,” the Conversion clock frequency gen-
Clock Generator 1 Conversion Clock Pin (CONV1) Frequency Select. When set to “1,” the frequency driven on to
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Clock Generator 1 Clock Rate Modifiers.
referenced to SYNC1 (C1REF set to “1”). This bit should be reset to “0” if C1REF is reset to “0.” When reset to
“0,” Clock Generator 1 is in normal lock mode where the Conversion clock will be frequency and phase locked to
SYNC1, and the Bit clock frequency is chosen using bits C1M7:0 and C1P200. When set to “1,” Clock Generator 1
is in video lock mode, where the Conversion clock frequency is selected using bits C1M7:0, and a Bit clock is not pro-
duced.
bit selects infinite PLL loop gain. This bit should nominally be reset to “0.” Setting it to “1” may enhance the PLL’s
ability to lock to certain SYNC1 inputs, but it may also increase conversion noise.
have a frequency that is 200 Hertz greater than the frequency selected through bit C1M7:0. This bit is ignored when
in Video Lock Mode (C1VID set to “1”). C1P200 only modifies the bit clock driven on the BIT1 pin.
erated will be 8/7 times the value programmed in Control Register Address 17. This bit is ignored when clocks are
referenced to SYNC1 (C1REF set to “1”).
the CONV1 pin will be 128 times the conversion rate. When reset to “0,” the frequency driven on to the CONV1 pin
will be the same as the conversion rate. C1C128 only modifies the clock frequency driven on the CONV1 pin.
When not in Video Lock Mode (C1REF and C1VID are not both set to “1”):
Bits C1M7:0 select the Bit clock rate which will be driven out on pin BIT1. Using the following table, the least sig-
nificant four bits (C1M3:0) are programmed to the desired Bit clock rate, and the most significant four bits
(C1M7:4) must be programmed to the Conversion clock rate established using Control Register Address 17 and the
C1X8/7 bit. If the actual Conversion clock differs from the value selected by C1M7:4, then the resultant Bit clock
will be different from the rate selected by the ratio of the C1M7:4 selected rate to the Control Register Address 17
plus the C1X8/7 bit actual rate.
C1M3:0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
*Bit clock frequencies listed will be increased by 200 Hz if C1P200 is set to “1.”
When C1M7:4 is programmed to “1111” and C1M3:0 is programmed to “1111,” the Bit clock rate will be 128 times
the Conversion rate.
When in Video Lock Mode (C1REF and C1VID are both set to “1”):
Bits C1M7:0 select the Conversion clock rate. The most significant bit (C1M7) must be set to indicate
the type of video lock, either NTSC or PAL. For an NTSC lock, C1M7 must be reset to “0,” and the SYNC1 pin
must receive the NTSC sync frequency (525 lines/frame 30 Hz
lock, C1M7 must be set to “1,” and the SYNC1 pin must receive the PAL sync frequency (625 lines/frame 25 Hz
frame rate
and the least significant four bits (C1M3:0) select a divisor. The Conversion clock created by Clock Generator 1 will
be the base divided by the divisor. The following tables list the possible choices for base and divisor.
15.625 kHz). The next three most significant bits (C1M6:4) select a desired base Conversion clock rate,
Bit Clock Frequency*
2,400
4,800
7,200
9,600
12,000
14,400
16,800
19,200
21,600
24,000
26,400
28,800
Reserved
Reserved
Reserved
See Below
Hertz
–38–
C1M7:4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1000/1001 frame rate
Conversion (Sample) Rate
7,200
8,400
9,000
9,600
11,200
12,000
12,800
7,200
9,000
9,600
12,000
Reserved
Reserved
Reserved
Reserved
See Below
15.734 kHz). For a PAL
8/7
8/7
8/7
Hertz
8/7
REV. 0