CS4202-JQZ Cirrus Logic Inc, CS4202-JQZ Datasheet - Page 33

• Manufacturer Part Number: CS4202-JQZ
• Description: IC AC 97 W/HEADPHONE AMP 48TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 18, 20 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPS
• Interface Type: Serial (5-Wire, I2S)
• Resolution: 18 bit, 20 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC/1 DAC
• Supply Current: 10 mA
• Thd Plus Noise: - 84 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1181

4.15
V
DRS
SPSR[1:0]
L
CC[6:0]
PRE
COPY
/AUDIO
PRO
Default
For a further discussion of the proper use of the channel status bits see application note AN22: Overview of Digital
Audio Interface Data Structures [3]
DS549PP2
D15
V
S/PDIF Control Register (Index 3Ah)
DRS SPSR1 SPSR0
D14
D13
Validity. The V bit is mapped to the V bit (bit 28) of every sub-frame. If this bit is ‘clear’, the
signal is suitable for conversion or processing.
Double Rate S/PDIF. The DRS bit is mapped to bit 27 of the channel status block. This bit
controls support for optional higher sample rate transmission. The CS4202 does not support
double rate S/PDIF transmission, therefore DRS is a read-only bit and always returns ‘0’.
S/PDIF Sample Rate. The SPSR[1:0] bits are mapped to bits 24 and 25 of the channel status
block. These bits control the S/PDIF transmitter clock rate. The CS4202 only supports trans-
mission at the standard 48 kHz rate, therefore SPSR[1:0] are read-only bits and always
return ‘10’.
Generation Status. The L bit is mapped to bit 15 of the channel status block. For category
codes 001xxxx, 0111xxx and 100xxxx, a value of ‘0’ indicates original material and a value of
‘1’ indicates a copy of original material. For all other category codes the definition of the L bit
is reversed.
Category Code. The CC[6:0] bits are mapped to bits 8-14 of the channel status block.
Data Pre-emphasis. The PRE bit is mapped to bit 3 of the channel status block. If the PRE bit
is ‘set’, 50/15 µs filter pre-emphasis is indicated. If the bit is ‘clear’, no pre-emphasis is indi-
cated.
Copyright. The COPY bit is mapped to bit 2 of the channel status block. If the COPY bit is ‘set’
copyright is not asserted and copying is permitted.
Audio / Non-Audio. The /AUDIO bit is mapped to bit 1 of the channel status block. If the
/AUDIO bit is ‘clear’, the data transmitted over S/PDIF is assumed to be digital audio. If the
/AUDIO bit is ‘set’, non-audio data is assumed.
PRO bit is ‘clear’, consumer use of the audio control block is indicated. If the bit is ‘set’, pro-
fessional use is indicated.
2000h
Professional/Consumer. The PRO bit is mapped to bit 0 of the channel status block. If the
D12
D11
L
CC6
D10
CC5
D9
CC4
D8
CC3
D7
CC2
D6
CC1
D5
CC0
D4
PRE
D3
COPY /AUDIO PRO
D2
CS4202
D1
D0
33