CS4202-JQZ Cirrus Logic Inc, CS4202-JQZ Datasheet - Page 31

• Manufacturer Part Number: CS4202-JQZ
• Description: IC AC 97 W/HEADPHONE AMP 48TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 18, 20 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPS
• Interface Type: Serial (5-Wire, I2S)
• Resolution: 18 bit, 20 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC/1 DAC
• Supply Current: 10 mA
• Thd Plus Noise: - 84 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1181

4.13
SPCV
SPSA[1:0]
SPDIF
VRA
Default
DS549PP2
D15
0
Extended Audio Status/Control Register (Index 2Ah)
D14
0
D13
0
subsystem, enabling the driver to determine if the currently programmed S/PDIF configura-
tion is supported. SPCV is always valid, independent of the S/PDIF enable bit status.
mitter. To satisfy AC ‘97 2.2 AMAP requirements, the default for these bits will depend on the
Codec ID as shown in Table 9 on page 30. See Table 8 on page 30 for all available Slot Map
settings.
SPDIF_OUT pin. The SPDIF bit routes the left and right channel data from the AC ’97 con-
troller or from the ADC output to the S/PDIF transmitter block. The actual data routed to the
S/PDIF block are controlled through the configuration of the SPSA[1:0] bits and the ASPM bit
in the AC Mode Control Register (Index 5Eh).
Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h). This bit must
be ‘set’ in order to use variable PCM playback or capture rates. The VRA bit also serves as
a powerdown for the DAC and ADC SRC blocks. Clearing VRA will reset the PCM Front DAC
Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h) to their default
values. The SRC data path is flushed and the Slot Request bits for the currently active DAC
slots will be fixed at ‘0’.
S/PDIF Configuration Valid. This read-only bit indicates the status of the S/PDIF transmitter
S/PDIF Slot Assignment. These bits control the mapping of output slots to the S/PDIF trans-
Enable Sony/Philips Digital Interface. This bit enables S/PDIF data transmission on the
Enable Variable Rate Audio. When ‘set’, the VRA bit allows access to the PCM Front DAC
0410h
D12
0
D11
0
SPCV
D10
D9
0
D8
0
D7
0
D6
0
SPSA1 SPSA0
D5
D4
D3
0
SPDIF
D2
CS4202
D1
0
VRA
D0
31