MPC5200BV400 Freescale Semiconductor, MPC5200BV400 Datasheet - Page 23

• Manufacturer Part Number: MPC5200BV400
• Description: IC MPU 32BIT 400MHZ 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC5200BV400

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Family Name: MPC52xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

2. Minimum times are measured at the package pin with the load circuit, and maximum times are measured with the load circuit
3. REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have
4. See the timing measurement conditions in the PCI Local Bus Specification.
For Measurement and Test Conditions, see the PCI Local Bus Specification.
1.3.8
The Local Plus Bus is the external bus interface of the MPC5200B. A maximum of eight configurable chip selects (CS) are
provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and MUXED. The reference clock is the
PCI CLK. The maximum bus frequency is 66 MHz.
Definition of Acronyms and Terms:
1.3.8.1
Freescale Semiconductor
as shown in the PCI Local Bus Specification.
a setup of 5 ns at 66 MHz. All other signals are bused.
•
•
•
•
•
•
Sym
t
t
CSN
CSA
t
t
t
t
t
t
t
t
t
3
4
5
6
7
8
9
1
2
WS = Wait State
DC = Dead Cycle
LB = Long Burst
DS = Data Size in Bytes
t
t
PCIck
IPBIck
DATA output valid before CS assertion
DATA output hold after CS negation
Local Plus Bus
OE assertion before CS assertion
= PCI clock period
OE negation before CS negation
ADDR valid before CS assertion
= IPBI clock period
Non-MUXed Mode
RW valid before CS assertion
ADDR hold after CS negation
RW hold after CS negation
PCI CLK to CS assertion
PCI CLK to CS negation
Figure 10. Timing Diagram—IPBI and PCI clock (example ratio: 4:1)
CS pulse width
Description
PCI CLK
IPBI CLK
Table 24. Non-MUXed Mode Timing
MPC5200B Data Sheet, Rev. 4
(2 + WS) × t
t
t
PCIck
IPBIck
t
t
t
t
t
t
IPBIck
IPBIck
IPBIck
IPBIck
IPBIck
PCIck
Min
4.6
2.9
—
—
PCIck
(2 + WS) × t
t
Max
10.6
PCIck
7.0
4.8
2.7
—
—
—
—
—
PCIck
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes SpecID
—
—
(1)
—
(2)
—
—
—
—
—
—
A7.10
A7.11
A7.1
A7.2
A7.3
A7.4
A7.5
A7.6
A7.7
A7.8
A7.9
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