XC5210-6PQ160C Xilinx Inc, XC5210-6PQ160C Datasheet - Page 33

• Manufacturer Part Number: XC5210-6PQ160C
• Description: IC FPGA 324 CLB'S 160-PQFP
• Manufacturer: Xilinx Inc
• Series: XC5200r

Specifications of XC5210-6PQ160C

• Number Of Logic Elements/cells: 1296
• Number Of Labs/clbs: 324
• Number Of I /o: 133
• Number Of Gates: 16000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 160-BQFP
• Dc: 0037
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Other names: 122-1147

Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the FPGA DIN input.
Each rising edge of the CCLK output increments the Serial
PROM internal address counter. The next data bit is put on
the SPROM data output, connected to the FPGA DIN pin.
The lead FPGA accepts this data on the subsequent rising
CCLK edge.
The lead FPGA then presents the preamble data—and all
data that overflows the lead device—on its DOUT pin.
There is an internal pipeline delay of 1.5 CCLK periods,
which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
In the bitstream generation software, the user can specify
Fast ConfigRate, which, starting several bits into the first
frame, increases the CCLK frequency by a factor of twelve.
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
Figure 30: Master Serial Mode Programming Switching Characteristics
In the two Master Parallel modes, the lead FPGA directly
addresses an industry-standard byte-wide EPROM, and
accepts eight data bits just before incrementing or decre-
menting the address outputs.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data—and all data that over-
flows the lead device—on its DOUT pin. There is an inter-
nal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data (and also changes the EPROM
address) until the falling CCLK edge that makes the LSB
(D0) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next FPGA in
the daisy chain accepts data on the subsequent rising
CCLK edge.
November 5, 1998 (Version 5.2)
CCLK
2. Master Serial mode timing is based on testing in slave mode.
Low until Vcc is valid.
Serial Data In
Serial DOUT
(Output)
(Output)
R
CCLK
DIN hold
DIN setup
Product Obsolete or Under Obsolescence
n – 3
Description
1
T
DSCK
n
n – 2
1
2
2 T
Symbol
XC5200 Series Field Programmable Gate Arrays
CKDS
n + 1
T
T
DSCK
CKDS
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output after con-
figuration. Using DONE can also avoid contention on DIN,
provided the DONE before I/O enable option is invoked.
Figure 28 on page 114
The leftmost device is in Master Serial mode.
Master Serial mode is selected by a <000> on the mode
pins (M2, M1, M0).
The value increases from a nominal 1 MHz, to a nominal 12
MHz. Be sure that the serial PROM and slaves are fast
enough to support this data rate. The Medium ConfigRate
option changes the frequency to a nominal 6 MHz.
XC2000, XC3000/A, and XC3100A devices do not support
the Fast or Medium ConfigRate options.
The SPROM CE input can be driven from either LDC or
The PROM address pins can be incremented or decre-
mented, depending on the mode pin settings. This option
allows the FPGA to share the PROM with a wide variety of
microprocessors and microcontrollers. Some processors
must boot from the bottom of memory (all zeros) while oth-
ers must boot from the top. The FPGA is flexible and can
load its configuration bitstream from either end of the mem-
ory.
Master Parallel Up mode is selected by a <100> on the
mode pins (M2, M1, M0). The EPROM addresses start at
00000 and increment.
Master Parallel Down mode is selected by a <110> on the
mode pins. The EPROM addresses start at 3FFFF and
decrement.
n – 1
Min
20
0
n + 2
shows a full master/slave system.
Max
n
X3223
Units
ns
ns
7-115
7