XC5210-6PQ160C Xilinx Inc, XC5210-6PQ160C Datasheet - Page 31

• Manufacturer Part Number: XC5210-6PQ160C
• Description: IC FPGA 324 CLB'S 160-PQFP
• Manufacturer: Xilinx Inc
• Series: XC5200r

Specifications of XC5210-6PQ160C

• Number Of Logic Elements/cells: 1296
• Number Of Labs/clbs: 324
• Number Of I /o: 133
• Number Of Gates: 16000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 160-BQFP
• Dc: 0037
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Other names: 122-1147

Note that in XC5200-Series devices, configuration data is
not inverted with respect to configuration as it is in XC2000
and XC3000 families.
Readback of Express mode bitstreams results in data that
does not resemble the original bitstream, because the bit-
stream format differs from other modes.
XC5200-Series Readback does not use any dedicated
pins,
RDBK.DATA, RDBK.RIP and RDBK.CLK) that can be
routed to any IOB. To access the internal Readback sig-
nals, place the READBACK library symbol and attach the
appropriate pad symbols, as shown in
After Readback has been initiated by a Low-to-High transi-
tion on RDBK.TRIG, the RDBK.RIP (Read In Progress)
output goes High on the next rising edge of RDBK.CLK.
Subsequent rising edges of this clock shift out Readback
data on the RDBK.DATA net.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit
(Low) of the first frame. The first two data bits of the first
frame are always High.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.
Readback Options
Readback options are: Read Capture, Read Abort, and
Clock Select. They are set with the bitstream generation
software.
Read Capture
When the Read Capture option is selected, the readback
data stream includes sampled values of CLB and IOB sig-
nals. The rising edge of RDBK.TRIG latches the inverted
values of the CLB outputs and the IOB output and input sig-
nals.
(interconnect and function generators) are not inverted, the
CLB and IOB output signals are inverted.
When the Read Capture option is not selected, the values
of the capture bits reflect the configuration data originally
written to those memory locations.
November 5, 1998 (Version 5.2)
MD0
Figure 27: Readback Schematic Example
IF UNCONNECTED,
DEFAULT IS CCLK
but
READ_TRIGGER
Note that while the bits describing configuration
uses
R
IBUF
four
Product Obsolete or Under Obsolescence
TRIG
CLK
internal
READBACK
DATA
RIP
nets
Figure
OBUF
READ_DATA
(RDBK.TRIG,
27.
X1786
MD1
XC5200 Series Field Programmable Gate Arrays
Read Abort
When the Read Abort option is selected, a High-to-Low
transition on RDBK.TRIG terminates the readback opera-
tion and prepares the logic to accept another trigger.
After an aborted readback, additional clocks (up to one
readback clock per configuration frame) may be required to
re-initialize the control logic. The status of readback is indi-
cated by the output control net RDBK.RIP. RDBK.RIP is
High whenever a readback is in progress.
Clock Select
CCLK is the default clock. However, the user can insert
another clock on RDBK.CLK. Readback control and data
are clocked on rising edges of RDBK.CLK. If readback
must be inhibited for security reasons, the readback control
nets are simply not connected.
Violating the Maximum High and Low Time
Specification for the Readback Clock
The readback clock has a maximum High and Low time
specification. In some cases, this specification cannot be
met. For example, if a processor is controlling readback,
an interrupt may force it to stop in the middle of a readback.
This necessitates stopping the clock, and thus violating the
specification.
The specification is mandatory only on clocking data at the
end of a frame prior to the next start bit. The transfer mech-
anism will load the data to a shift register during the last six
clock cycles of the frame, prior to the start bit of the follow-
ing frame. This loading process is dynamic, and is the
source of the maximum High and Low time requirements.
Therefore, the specification only applies to the six clock
cycles prior to and including any start bit, including the
clocks before the first start bit in the readback data stream.
At other times, the frame data is already in the register and
the register is not dynamic. Thus, it can be shifted out just
like a regular shift register.
The user must precisely calculate the location of the read-
back data relative to the frame. The system must keep
track of the position within a data frame, and disable inter-
rupts before frame boundaries. Frame lengths and data for-
mats are listed in
Readback with the XChecker Cable
The XChecker Universal Download/Readback Cable and
Logic Probe uses the readback feature for bitstream verifi-
cation. It can also display selected internal signals on the
PC or workstation screen, functioning as a low-cost in-cir-
cuit emulator.
The readback signals are located in the lower-left corner of
the device.
Table 11
and
Table
12.
7-113
7