XC5210-6PQ160C Xilinx Inc, XC5210-6PQ160C Datasheet - Page 19

• Manufacturer Part Number: XC5210-6PQ160C
• Description: IC FPGA 324 CLB'S 160-PQFP
• Manufacturer: Xilinx Inc
• Series: XC5200r

Specifications of XC5210-6PQ160C

• Number Of Logic Elements/cells: 1296
• Number Of Labs/clbs: 324
• Number Of I /o: 133
• Number Of Gates: 16000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 160-BQFP
• Dc: 0037
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Other names: 122-1147

Even if the boundary scan symbol is used in a schematic,
the input pins TMS, TCK, and TDI can still be used as
inputs to be routed to internal logic. Care must be taken not
to force the chip into an undesired boundary scan state by
inadvertently applying boundary scan input patterns to
these pins. The simplest way to prevent this is to keep
TMS High, and then apply whatever signal is desired to TDI
and TCK.
Avoiding Inadvertent Boundary Scan
If TMS or TCK is used as user I/O, care must be taken to
ensure that at least one of these pins is held constant dur-
ing configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.
To prevent activation of boundary scan during configura-
tion, do either of the following:
• TMS: Tie High to put the Test Access Port controller
• TCK: Tie High or Low—do not toggle this clock input.
For more information regarding boundary scan, refer to the
Xilinx Application Note XAPP 017, “ Boundary Scan in
XC4000 and XC5200 Devices .“
Power Distribution
Power for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated Vcc and Ground ring sur-
rounding the logic array provides power to the I/O drivers,
as shown in
Ground lines supplies the interior logic of the device.
This power distribution grid provides a stable supply and
ground for all internal logic, providing the external package
power pins are all connected and appropriately decoupled.
November 5, 1998 (Version 5.2)
in a benign RESET state
Figure 20: Boundary Scan Schematic Example
User Logic
From
Figure
R
21. An independent matrix of Vcc and
Optional
Product Obsolete or Under Obsolescence
TDI
TMS
TCK
TDO1
TDO2
BSCAN
IBUF
UPDATE
RESET
SHIFT
DRCK
SEL1
SEL2
IDLE
TDO
To User
Logic
To User
Logic
X9000
XC5200 Series Field Programmable Gate Arrays
Pin Descriptions
There are three types of pins in the XC5200-Series
devices:
• Permanently dedicated pins
• User I/O pins that can have special functions
• Unrestricted user-programmable I/O pins.
Before and during configuration, all outputs not used for the
configuration process are 3-stated and pulled high with a
20 k
After configuration, if an IOB is unused it is configured as
an input with a 20 k
Device pins for XC5200-Series devices are described in
Table
seven configuration modes are summarized in
Typically, a 0.1 F capacitor connected near the Vcc and
Ground pins of the package will provide adequate decou-
pling.
Output buffers capable of driving/sinking the specified 8 mA
loads under specified worst-case conditions may be capa-
ble of driving/sinking up to 10 times as much current under
best case conditions.
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the Ground pads. The I/O Block
output buffers have a slew-rate limited mode (default)
which should be used where output rise and fall times are
not speed-critical.
Figure 21: XC5200-Series Power Distribution
Vcc
9. Pin functions during configuration for each of the
- 100 k
pull-up resistor.
- 100 k
GND
GND
pull-up resistor.
Vcc
Logic
Power Grid
Ground and
Vcc Ring for
I/O Drivers
“Pin Func-
X5422
7-101
7