XC5VLX30-2FF324I Xilinx Inc, XC5VLX30-2FF324I Datasheet - Page 380

• Manufacturer Part Number: XC5VLX30-2FF324I
• Description: IC FPGA VIRTEX-5 30K 324FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX30-2FF324I

• Number Of Logic Elements/cells: 30720
• Number Of Labs/clbs: 2400
• Total Ram Bits: 1179648
• Number Of I /o: 220
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-BBGA, FCBGA
• For Use With: HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 8: Advanced SelectIO Logic Resources
380
Timing Characteristics of 4:1 DDR 3-State Controller Serialization
The second word IJKLMNOP is sampled into the master and slave OSERDES from the D1–
D6 and D3–D4 inputs, respectively.
Clock Event 4
Between Clock Events 3 and 4, the entire word ABCDEFGH is transmitted serially on OQ,
a total of eight bits transmitted in one CLKDIV cycle.
The data bit I appears at OQ four CLK cycles after IJKLMNOP is sampled into the
OSERDES. This latency is consistent with the
OSERDES latency of four CLK cycles.
The operation of a 3-State Controller is illustrated in
case shown in a bidirectional system where the IOB must be frequently 3-stated.
X-Ref Target - Figure 8-19
OBUFT.O
CLKDIV
Figure 8-19: OSERDES Data Flow and Latency in 4:1 DDR Mode
CLK
OQ
TQ
D1
D2
D3
D4
T1
T2
T3
T4
www.xilinx.com
1
1
1
1
A
B
C
D
Event 1
Clock
A B C D E F G H
G
E
H
F
0
0
1
0
Table 8-10
Clock
Event 2
E F
Figure
K
J
L
I
listing of a 8:1 DDR mode
H
8-19. The example is a 4:1 DDR
I J K L
1
1
1
1
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
UG190_8_19_100307