XC5VLX30-2FF324I Xilinx Inc, XC5VLX30-2FF324I Datasheet - Page 217

• Manufacturer Part Number: XC5VLX30-2FF324I
• Description: IC FPGA VIRTEX-5 30K 324FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX30-2FF324I

• Number Of Logic Elements/cells: 30720
• Number Of Labs/clbs: 2400
• Total Ram Bits: 1179648
• Number Of I /o: 220
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-BBGA, FCBGA
• For Use With: HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

SelectIO Resources
I/O Tile Overview
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Input/output characteristics and logic resources are covered in three consecutive chapters.
Chapter 6, SelectIO Resources
input receivers, and gives detailed examples of many standard interfaces.
SelectIO Logic
Data-Rate (DDR) operation, and the programmable input delay (IDELAY).
Advanced SelectIO Logic
An I/O tile contains two IOBs, two ILOGICs, two OLOGICs, and two IODELAYs.
Figure 6-1
X-Ref Target - Figure 6-1
shows a Virtex-5 FPGA I/O tile.
Resources, describes the input and output data registers and their Double-
(Chapter 7)
(Chapter 7)
(Chapter 8)
(Chapter 7)
(Chapter 8)
(Chapter 7)
(Chapter 8)
(Chapter 7)
(Chapter 8)
(Chapter 7)
OSERDES
OSERDES
www.xilinx.com
Resources, describes the data serializer/deserializer (SERDES).
ISERDES
ISERDES
IODELAY
IODELAY
OLOGIC
OLOGIC
Figure 6-1: Virtex-5 FPGA I/O Tile
ILOGIC
ILOGIC
or
or
or
or
describes the electrical behavior of the output drivers and
(Chapter 6)
(Chapter 6)
IOB
IOB
ug190_6_01_041106
Pad
Pad
Chapter 6
Chapter 7,
Chapter 8,
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