XC5VLX30-2FF324I Xilinx Inc, XC5VLX30-2FF324I Datasheet - Page 37

• Manufacturer Part Number: XC5VLX30-2FF324I
• Description: IC FPGA VIRTEX-5 30K 324FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX30-2FF324I

• Number Of Logic Elements/cells: 30720
• Number Of Labs/clbs: 2400
• Total Ram Bits: 1179648
• Number Of I /o: 220
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-BBGA, FCBGA
• For Use With: HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

X-Ref Target - Figure 1-16
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
CE
I0
I1
O
S
1
at I0
T
BCCKO_O
BUFGMUX_CTRL with a Clock Enable
A BUFGMUX_CTRL with a clock enable BUFGCTRL configuration allows the user to
choose between the incoming clock inputs. If needed, the clock enable is used to disable
the output.
shows the timing diagram.
X-Ref Target - Figure 1-15
In
•
•
•
•
Figure 1-16: BUFGMUX_CTRL with a CE Timing Diagram
Figure
At time event 1, output O uses input I0.
Before time event 2, S is asserted High.
At time T
to Low transition of I0 followed by a High to Low transition of I1 is completed.
At time T
switched Low and kept at Low after a High to Low transition of I1 is completed.
1-16:
CE
I1
I0
S
Figure 1-15
BCCKO_O
BCCCK_CE
Figure 1-15: BUFGMUX_CTRL with a CE and BUFGCTRL
BUFGMUX_CTRL+CE
2
Design Example
Begin I1
, after time event 2, output O uses input I1. This occurs after a High
, before time event 3, CE is asserted Low. The clock output is
illustrates the BUFGCTRL usage design example and
T
BCCKO_O
www.xilinx.com
O
CE
S
GND
GND
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
Global Clocking Resources
Clock Off
UG190_1_15_052009
3
T
BCCCK_CE
Figure 1-16
ug190_1_16_040907
O
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