XC5VLX30-2FF324I Xilinx Inc, XC5VLX30-2FF324I Datasheet - Page 22

• Manufacturer Part Number: XC5VLX30-2FF324I
• Description: IC FPGA VIRTEX-5 30K 324FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX30-2FF324I

• Number Of Logic Elements/cells: 30720
• Number Of Labs/clbs: 2400
• Total Ram Bits: 1179648
• Number Of I /o: 220
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-BBGA, FCBGA
• For Use With: HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Preface: About This Guide
Additional Support Resources
Typographical Conventions
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To find additional documentation, see the Xilinx website at:
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
This document uses the following typographical conventions. An example illustrates each
convention.
Italic font
Virtex-5 FPGA Configuration Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.
Virtex-5 FPGA System Monitor User Guide
The System Monitor functionality available in all the Virtex-5 devices is outlined in
this guide.
Virtex-5 FPGA Packaging and Pinout Specification
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
Virtex-5 FPGA PCB Designer’s Guide
This guide provides information on PCB design for Virtex-5 devices, with a focus on
strategies for making design decisions at the PCB and interface level.
http://www.xilinx.com/support/documentation/index.htm.
http://www.xilinx.com/support.
Convention
References to other documents
Emphasis in text
www.xilinx.com
Meaning or Use
See the Virtex-5 FPGA Configuration
Guide for more information.
The address (F) is asserted after
clock event 2.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Example