EP2C20F484C8 Altera, EP2C20F484C8 Datasheet - Page 97

• Manufacturer Part Number: EP2C20F484C8
• Description: IC CYCLONE II FPGA 20K 484-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C20F484C8

• Number Of Logic Elements/cells: 18752
• Number Of Labs/clbs: 1172
• Total Ram Bits: 239616
• Number Of I /o: 315
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 18752
• # I/os (max): 315
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 18752
• Ram Bits: 239616
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• For Use With: P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1365; EP2C20F484C8

Altera Corporation
February 2008
Notes to
(1)
(2)
1.5-V HSTL class I
1.5V HSTL class II
Table 5–7. DC Characteristics of User I/O Pins Using Single-Ended Standards
I/O Standard
The values in this table are based on the conditions listed in
This specification is supported across all the programmable drive settings available as shown in the
Architecture
Table
5–7:
chapter of the Cyclone II Device Handbook.
I
OL
16
(mA)
Differential I/O Standards
The RSDS and mini-LVDS I/O standards are only supported on output
pins. The LVDS I/O standard is supported on both receiver input pins
and transmitter output pins.
1
Figure 5–1
standards (LVDS, LVPECL, differential 1.5-V HSTL class I and II,
differential 1.8-V HSTL class I and II, differential SSTL-2 class I and II, and
differential SSTL-18 class I and II).
8
Test Conditions
For more information on how these differential I/O standards
are implemented, refer to the
Cyclone II Devices
shows the receiver input waveforms for all differential I/O
I
OH
–16
–8
(mA)
chapter of the Cyclone II Device Handbook.
Tables 5–2
Maximum V
DC Characteristics and Timing Specifications
0.4
0.4
Cyclone II Device Handbook, Volume 1
and 5–6.
High-Speed Differential Interfaces in
Voltage Thresholds
OL
(V)
Notes
(1),
Minimum V
V
V
(2)
C C I O
C C I O
(Part 2 of 2)
Cyclone II
– 0.4
– 0.4
OH
(V)
5–7