EP2C20F484C8 Altera, EP2C20F484C8 Datasheet - Page 25

• Manufacturer Part Number: EP2C20F484C8
• Description: IC CYCLONE II FPGA 20K 484-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C20F484C8

• Number Of Logic Elements/cells: 18752
• Number Of Labs/clbs: 1172
• Total Ram Bits: 239616
• Number Of I /o: 315
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 18752
• # I/os (max): 315
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 18752
• Ram Bits: 239616
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• For Use With: P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1365; EP2C20F484C8

Altera Corporation
February 2007
Figure 2–9. Register Chain Interconnects
The C4 interconnects span four LABs, M4K blocks, or embedded
multipliers up or down from a source LAB. Every LAB has its own set of
C4 interconnects to drive either up or down.
interconnect connections from an LAB in a column. The C4 interconnects
can drive and be driven by all types of architecture blocks, including
PLLs, M4K memory blocks, embedded multiplier blocks, and column
and row IOEs. For LAB interconnection, a primary LAB or its LAB
neighbor (see
interconnects can drive each other to extend their range as well as drive
row interconnects for column-to-column connections.
Interconnect
Adjacent LE
Carry Chain
Routing to
Figure
Local
2–10) can drive a given C4 interconnect. C4
Local Interconnect
Routing Among LEs
in the LAB
Cyclone II Device Handbook, Volume 1
LE 10
LE 16
LE 1
LE 2
LE 3
LE 4
LE 5
LE 6
LE 7
LE 8
LE 9
LE 11
LE 12
LE13
LE 14
LE 15
Figure 2–10
Register Chain
Routing to Adjacent
LE's Register Input
Cyclone II Architecture
shows the C4
2–13