EP2C20F484C8 Altera, EP2C20F484C8 Datasheet - Page 64

• Manufacturer Part Number: EP2C20F484C8
• Description: IC CYCLONE II FPGA 20K 484-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C20F484C8

• Number Of Logic Elements/cells: 18752
• Number Of Labs/clbs: 1172
• Total Ram Bits: 239616
• Number Of I /o: 315
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 18752
• # I/os (max): 315
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 18752
• Ram Bits: 239616
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• For Use With: P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1365; EP2C20F484C8

I/O Structure & Features
2–52
Cyclone II Device Handbook, Volume 1
3.3-V LVTTL and LVCMOS
(1)
2.5-V LVTTL and LVCMOS
1.8-V LVTTL and LVCMOS
1.5-V LVCMOS
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
HSTL-18 class I
HSTL-18 class II
HSTL-15 class I
HSTL-15 class II
PCI and PCI-X
Differential SSTL-2 class I or
class II
Differential SSTL-18 class I
or class II
Table 2–17. Cyclone II Supported I/O Standards & Constraints (Part 1 of 2)
I/O Standard
(1) (3)
Advanced I/O Standard Support
Table 2–17
which I/O pins support them.
Single ended
Single ended
Single ended
Single ended
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Single ended
Pseudo
differential
Pseudo
differential
Type
(4)
(4)
shows the I/O standards supported by Cyclone II devices and
3.3 V/
3.3 V/
1.8 V/
1.8 V/
Input Output
2.5 V
2.5 V
1.5 V
1.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
3.3 V
2.5 V
1.8 V
V
(5)
(5)
CCIO
Level
3.3 V
2.5 V
1.8 V
1.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
3.3 V
2.5 V
1.8 V
(5)
(5)
CLK,
DQS
Top & Bottom
v
v
v
v
v
v
v
v
v
v
v
v
v
v
(6)
(6)
I/O Pins
User I/O
Pins
v
v
v
v
v
v
v
v
v
v
v
v
CLK,
DQS
v
v
v
v
v
v
v
(2)
v
(2)
v
(2)
v
v
(6)
v
(6)
PLL_OUT
Side I/O Pins
v
Altera Corporation
v
v
v
v
v
v
v
v
v
v
v
(2)
(2)
(2)
(7)
February 2007
User I/O
Pins
v
v
v
v
v
v
v
v
v
v
(2)
(2)
(2)