ADSP-21375KSZ-2B Analog Devices Inc, ADSP-21375KSZ-2B Datasheet - Page 30

• Manufacturer Part Number: ADSP-21375KSZ-2B
• Description: IC DSP 32BIT 266MHZ 208-MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21375KSZ-2B

• Interface: DAI, DPI
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (256 kB)
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21371/ADSP-21375
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 28. Memory Write—Bus Master
1
2
3
4
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in AMICTLx register) × t
in AMICTLx register) × t
ACK delay/setup: System must meet t
The falling edge of MSx is referenced.
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
See
DAAK
DSAK
DAWH
DAWL
WW
DDWH
DWHA
DWHD
DATRWH
WWR
DDWR
WDE
user must meet t
Test Conditions on Page 46
ADDRESS
MSx
DATA
ACK
WR
RD
DAAK
ACK Delay from Address, Selects
ACK Delay from WR Low
Address, Selects to WR Deasserted
Address, Selects to WR Low
WR Pulse Width
Data Setup Before WR High
Address Hold After WR Deasserted
Data Hold After WR Deasserted
Data Disable After WR Deasserted
WR High to WR, RD Low
Data Disable Before RD Low
WR Low to Data Enabled
or t
DSAK
SDCLK
.
for calculation of hold times given capacitive and dc loads.
DAAK
, or t
t
t
DAWL
DAAK
DSAK
t
WDE
, for deassertion of ACK (low). For asynchronous assertion of ACK (high)
1, 3
2
1, 2
Figure 18. Memory Write—Bus Master
t
DSAK
4
Rev. B | Page 30 of 52 | June 2008
2
1.2 V, 266 MHz
Min
t
t
W – 1.3
t
H + 0.15
H + 0.02
t
t
2t
t
SDCLK
SDCLK
SDCLK
SDCLK
SDCLK
SDCLK
SDCLK
SDCLK
t
– 3.6 + W
– 2.7
DAWH
– 1.5+ H
– 3.0 + W
– 1.37 + H t
– 4.1
H = (number of hold cycles specified
– 5.1
t
WW
t
DDWH
Max
t
W – 7.1
SDCLK
SDCLK
– 10.1 + W
+ 4.9+ H
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
DATRWH
t
DWHD
t
t
t
WWR
DWHA
DDWR