ADSP-21375KSZ-2B Analog Devices Inc, ADSP-21375KSZ-2B Datasheet - Page 2

• Manufacturer Part Number: ADSP-21375KSZ-2B
• Description: IC DSP 32BIT 266MHZ 208-MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21375KSZ-2B

• Interface: DAI, DPI
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (256 kB)
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21371/ADSP-21375
KEY FEATURES
At 266 MHz (3.75 ns) core instruction rate, the ADSP-21371/
ADSP-21371—1M bit on-chip SRAM for simultaneous access
ADSP-21375—0.5M bit on-chip SRAM for simultaneous
Dual data address generators (DAGs) with modulo and bit-
Zero-overhead looping with single-cycle loop setup, provid-
Single instruction multiple data (SIMD) architecture provides
Transfers between memory and core at a sustained
INPUT/OUTPUT FEATURES
ADSP-21371—DMA controller supports
ADSP-21371—32-bit wide external port provides glueless
Digital audio interface (DAI) includes eight serial ports
Digital peripheral interface (DPI) includes, two timers, one
8 dual data line serial ports (ADSP-21371) that operate at up
ADSP-21375 performs 1.596 GFLOPs/533 MMACs
by the core processor and DMA; 4M bit on-chip, mask-pro-
grammable ROM
access by the core processor and DMA; 2M bit on-chip,
mask-programmable ROM
reverse addressing
ing efficient program sequencing
2 computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
Parallelism in buses and computational units allows
4.25G bytes/second bandwidth at 266 MHz core instruc-
tion rate
32 DMA channels for transfers between ADSP-21371 inter-
32-bit DMA transfers at peripheral clock speed, in parallel
connection to both synchronous (SDRAM) and asynchro-
nous memory devices
(ADSP-21371), four precision clock generators, an input
data port, an S/PDIF transceiver, and a signal routing unit
UART, two SPI ports, and a 2-wire interface port
to 50 Mbps on each data line — each has a clock, frame
sync, and two data lines that can be configured as either a
receiver or transmitter pair
the assembly level
single cycle executions (with or without SIMD) of a multi-
ply operation, an ALU operation, a dual memory read or
write, and an instruction fetch
nal memory and a variety of peripherals
with full-speed processor execution
Programmable wait state options: 2 to 31 SDCLK cycles
Delay-line DMA engine maintains circular buffers in
SDRAM accesses at 133 MHz and asynchronous accesses
4 memory select lines allows multiple external memory
Outputs of PCGs A and B can be routed through DAI pin
Outputs of PCGs C and D can be driven on to DAI as well
at 44.4 MHz
devices
as DPI pins
external memory with tap/offset based reads
—
PROCESSOR CORE
Rev. B | Page 2 of 52 | June 2008
TDM support for telecommunications interfaces including
Up to 16 TDM stream support, each with 128 channels per
Companding selection on a per channel basis in TDM mode
Input data port, configurable as eight channels of serial data
Signal routing unit provides configurable and flexible con-
2 muxed flag/IRQ lines
1 muxed flag/IRQ/MS pin
1 muxed flag/Timer expired line /MS pin
ADSP-21371—S/PDIF-compatible digital audio
Left-justified, I
Pulse-width modulation provides
ROM-based security features include
PLL has a wide variety of software and hardware multi-
Newly introduced “Running Reset” feature that allows a reset
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 208-lead LQFP_EP package (see
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
frame (ADSP-21371)
or seven channels of serial data and up to a 20-bit wide
parallel data channel (ADSP-21371)
nections between the various peripherals and the DAI/DPI
components
receiver/transmitter supports EIAJ CP-340 (CP-1201), IEC-
958, AES/EBU standards
18-, 20-, or 24-bit word widths (transmitter)
16 PWM outputs configured as four groups of four outputs
supports center-aligned or edge-aligned PWM waveforms
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
plier/divider ratios
of the processor core and peripherals, but without reset-
ting the PLL and SDRAM controller or performing a boot
on Page
access under program control to sensitive code
52)
2
S or right-justified serial data input with 16-,
Ordering Guide