MSC8126MP8000 Freescale Semiconductor, MSC8126MP8000 Datasheet - Page 40

• Manufacturer Part Number: MSC8126MP8000
• Description: DSP 16BIT 500MHZ MULTI 431FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of MSC8126MP8000

• Interface: DSI, Ethernet, RS-232
• Clock Rate: 500MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 90°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• For Use With: MSC8126ADSE - KIT ADVANCED DEV SYSTEM 8126
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Hardware Design Considerations
3
The following sections discuss areas to consider when the MSC8126 device is designed into a system.
3.1
Use the following guidelines for start-up and power-down sequences:
Note:
External voltage applied to any input line must not exceed the I/O supply
power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes.
This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per input pin per device in the
system during start-up.
During the power-up sequence, if V
device ESD protection circuits to the V
by more than 0.8 V. Design the power supply to prevent or minimize this effect using one of the following optional methods:
After power-up,
3.2
When used as a drop-in replacement in MSC8102 applications or when implementing a new design, use the guidelines
described in Migrating Designs from the MSC8102 to the MSC8122 (AN2716) and the MSC8126 Design Checklist (AN3374
for optimal system performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937)
provides detailed design information. See Section 2.5.2 for start-up timing specifications.
Figure 33 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the
decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on
the package pins should not drop below the minimum specified voltage level even for a very short spikes. This can be achieved
by using the following guidelines:
40
•
•
•
•
•
•
Assert
required minimum power levels. This can be implemented via weak pull-down resistors.
CLKIN
start toggling before the deassertion of
If possible, bring up
V
voltage levels down together. If that is not possible reverse the power-up sequence, with
then
This recommended power sequencing for the MSC8126 is different from the MSC8102. See Section 2.5.2 for
start-up timing specifications.
Never allow V
Design the V
current. Such a design yields an initial V
For the core supply, use a voltage regulator rated at 1.2 V with nominal rating of at least 3 A. This rating does not
reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has
better voltage recovery time than supplies with lower current ratings.
DDH
Hardware Design Considerations
Start-up Sequencing Recommendations
Power Supply Design Considerations
V
.
DD
V
PORESET
can be held low or allowed to toggle during the beginning of the power-up sequence. However,
V
DDH
/
DDH
V
CCSYN
should not exceed
DDH
must not exceed
DD
.
to exceed V
supply to prevent reverse current flow by adding a minimum 10 Ω resistor to GND to limit the
and
V
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
DD
TRST
/
V
DD
CCSYN
before applying power and keep the signals driven low until the power reaches the
DDH
DDH
rises before V
V
V
DD
DD
and
supply. The ESD protection diode can allow this to occur when V
/
/
+ 0.8V.
V
V
CCSYN
CCSYN
V
PORESET
DDH
DDH
by more than 2.6 V.
together. If it is not possible, raise
until
DDH
level of V
V
(see Figure 6), current can pass from the V
and after both power supplies have reached nominal voltage levels.
DD
/
V
CCSYN
DD
– 0.8 V before it is enabled.
reaches its nominal voltage level. Similarly, bring both
V
DDH
by more than 0.8 V at any time, including during
V
DD
/
V
CCSYN
V
DDH
first and then bring up
Freescale Semiconductor
DD
going down first and
supply through the
DD
exceeds V
CLKIN
must
DDH