MSC8126MP8000 Freescale Semiconductor, MSC8126MP8000 Datasheet - Page 24

• Manufacturer Part Number: MSC8126MP8000
• Description: DSP 16BIT 500MHZ MULTI 431FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of MSC8126MP8000

• Interface: DSI, Ethernet, RS-232
• Clock Rate: 500MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 90°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• For Use With: MSC8126ADSE - KIT ADVANCED DEV SYSTEM 8126
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Electrical Characteristics
24
Notes:
No.
32a
32b
32d
33a
33b
35a
35b
32c
31
34
PSDVAL/TEA/TA max delay from the 50% level of the REFCLK
rising edge
Address bus max delay from the 50% level of the REFCLK rising
edge
•
•
Address attributes: TT[0–1]/TBST/TSZ/GBL max delay from the 50%
level of the REFCLK rising edge
Address attributes: TT[2–4]/TC max delay from the 50% level of the
REFCLK rising edge
BADDR max delay from the 50% level of the REFCLK rising edge
Data bus max delay from the 50% level of the REFCLK rising edge
•
•
DP max delay from the 50% level of the REFCLK rising edge
•
•
Memory controller signals/ALE/CS[0–4] max delay from the 50%
level of the REFCLK rising edge
DBG/BG/BR/DBB max delay from the 50% level of the REFCLK
rising edge
AACK/ABB/TS/CS[5–7] max delay from the 50% level of the
REFCLK rising edge
1.
2.
3.
4.
Multi-master mode (SIUBCR[EBM] = 1)
Single-master mode (SIUBCR[EBM] = 0)
Data-pipeline mode
Non-pipeline mode
Data-pipeline mode
Non-pipeline mode
Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except
where otherwise specified.
Except for specification 30, which is specified for a 10 pF load, all timings in this table are specified for a 20 pF load.
Decreasing the load results in a timing decrease at the rate of 0.3 ns per 5 pF decrease in load. Increasing the load results in
a timing increase at the rate of 0.15 ns per 5 pF increase in load.
The maximum bus frequency depends on the mode:
In 60x-compatible mode connected to another MSC8126 device, the frequency is determined by adding the input and output
longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other
influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on.
• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8126.
• To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing a 1 to the
SIUMCR[BDD] bit. See the SIU chapter in the MSC8122 Reference Manual for details.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Characteristic
Table 15. AC Timing for SIU Outputs (continued)
Ref = CLKIN
133
Value for Bus Speed in MHz
4.9
5.5
4.2
5.1
5.7
4.2
3.9
6.1
5.3
6.5
4.2
4.7
4.5
166
4.9
5.5
3.9
5.1
5.7
4.2
3.7
6.1
5.3
6.5
3.9
4.7
4.5
Ref = CLKOUT
Freescale Semiconductor
133
5.8
6.4
5.1
6.0
6.6
5.1
4.8
7.0
6.2
7.4
5.1
5.6
5.4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns