USB3280-AEZG-TR Standard Microsystems (SMSC), USB3280-AEZG-TR Datasheet - Page 35

• Manufacturer Part Number: USB3280-AEZG-TR
• Manufacturer: Standard Microsystems (SMSC)

Hi-Speed USB Device PHY with UTMI Interface
Datasheet
SMSC USB3280
PARAMETER
TIMING
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
HS Handshake begins. DP pull-up enabled, HS
terminations disabled.
Device asserts Chirp K on the bus.
Device removes Chirp K from the bus. 1 ms
minimum width.
Downstream facing port asserts Chirp K on the
bus.
Downstream facing port toggles Chirp K to Chirp J
on the bus.
Downstream facing port toggles Chirp J to Chirp K
on the bus.
Device detects downstream port chirp.
Chirp detected by the device. Device removes DP
pull-up and asserts HS terminations, reverts to HS
default state and waits for end of reset.
Terminate host port Chirp K-J sequence (Repeating
T4 and T5)
The earliest time at which host port may end reset.
The latest time, at which the device may remove
the DP pull-up and assert the HS terminations,
reverts to HS default state.
Figure 8.5 HS Detection Handshake Timing Behavior (HS Mode)
DESCRIPTION
Table 8.7 Reset Timing Values
DATASHEET
35
0 (reference)
T0 < T1 < HS Reset T0 + 6.0ms
T0 + 1.0ms < T2 <
HS Reset T0 + 7.0ms
T2 < T3 < T2+100µs
T3 + 40µs < T4 < T3 + 60µs
T4 + 40µs < T5 < T4 + 60µs
T6
T6 < T7 < T6 + 500µs
T9 - 500µs < T8 < T9 - 100µs
HS Reset T0 + 10ms
VALUE
Revision 1.5 (11-15-07)