USB3280-AEZG-TR Standard Microsystems (SMSC), USB3280-AEZG-TR Datasheet - Page 31

• Manufacturer Part Number: USB3280-AEZG-TR
• Manufacturer: Standard Microsystems (SMSC)

Hi-Speed USB Device PHY with UTMI Interface
Datasheet
SMSC USB3280
8.6
PARAMETER
HS Reset T0
TIMING
T1
T2
T3
T4
Suspend Detection
If a HS device detects SE0 asserted on the bus for more than 3ms (T1), it reverts to FS mode. This
enables the FS pull-up on the DP line in an attempt to assert a continuous FS J state on the bus. The
SIE must then check LINESTATE for the J condition. If J is asserted at time T2, then the upstream
port is asserting a soft SE0 and the USB is in a J state indicating a suspend condition. By time T4
the device must be fully suspended.
End of last bus activity, signaling either a reset
or a SUSPEND.
The time at which the device must place itself
in FS mode after bus activity stops.
SIE samples LINESTATE. If LINESTATE = 'J',
then the initial SE0 on the bus (T0 - T1) had
been due to a Suspend state and the SIE
remains in HS mode.
The earliest time where a device can issue
Resume signaling.
The latest time that a device must actually be
suspended, drawing no more than the
suspend current from the bus.
Figure 8.2 Suspend Timing Behavior (HS Mode)
Table 8.5 Suspend Timing Values (HS Mode)
DESCRIPTION
DATASHEET
31
0 (reference)
HS Reset T0 + 3. 0ms < T1 < HS Reset T0
+ 3.125ms
T1 + 100 µs < T2 <
T1 + 875µs
HS Reset T0 + 5ms
HS Reset T0 + 10ms
VALUE
Revision 1.5 (11-15-07)