USB3280-AEZG-TR Standard Microsystems (SMSC), USB3280-AEZG-TR Datasheet - Page 10

• Manufacturer Part Number: USB3280-AEZG-TR
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.5 (11-15-07)
RXACTIVE
RXERROR
TXREADY
DATA[7:0]
TXVALID
RXVALID
NAME
(TXR)
(RXV)
(RXA)
(RXE)
(TXV)
(D7)
(D0)
NAME
RBIAS
NAME
.
.
.
XI/XO
DM
(RB)
DP
DIRECTION
Bidirectional
Output
Output
Output
Output
Input
DIRECTION
DIRECTION
Input
Input
I/O
I/O
Table 4.4 Biasing and Clock Oscillator Signals
ACTIVE
LEVEL
High
High
High
High
High
High
ACTIVE
LEVEL
ACTIVE
LEVEL
N/A
N/A
Table 4.2 Data Interface Signals
N/A
N/A
Table 4.3 USB I/O Signals
DESCRIPTION
Data bus. 8-bit Bidirectional mode.
Transmit Valid. Indicates that the DATA bus is valid for transmit. The
assertion of TXVALID initiates the transmission of SYNC on the USB
bus. The negation of TXVALID initiates EOP on the USB.
Control inputs (OPMODE[1:0], TERMSELECT,XCVRSELECT) must
not be changed on the de-assertion or assertion of TXVALID. The
PHY must be in a quiescent state when these inputs are changed.
Transmit Data Ready. If TXVALID is asserted, the SIE must always
have data available for clocking into the TX Holding Register on the
rising edge of CLKOUT. TXREADY is an acknowledgement to the
SIE that the transceiver has clocked the data from the bus and is
ready for the next transfer on the bus. If TXVALID is negated,
TXREADY can be ignored by the SIE.
Receive Data Valid. Indicates that the DATA bus has received valid
data. The Receive Data Holding Register is full and ready to be
unloaded. The SIE is expected to latch the DATA bus on the rising
edge of CLKOUT.
Receive Active. Indicates that the receive state machine has
detected Start of Packet and is active.
Receive Error.
0: Indicates no error.
1: Indicates a receive error has been detected.
This output is clocked with the same timing as the receive DATA lines
and can occur at anytime during a transfer.
DATASHEET
USB Positive Data Pin.
USB Negative Data Pin.
External 1% bias resistor. Requires a 12kΩ resistor to ground.
Used for setting HS transmit current level and on-chip
termination impedance.
External crystal. 24MHz crystal connected from XI to XO.
TXVALID
0
1
10
DATA[7:0]
output
input
Hi-Speed USB Device PHY with UTMI Interface
DESCRIPTION
DESCRIPTION
SMSC USB3280
Datasheet