IXP2400 Intel, IXP2400 Datasheet - Page 25

• Manufacturer Part Number: IXP2400
• Manufacturer: Intel

Specifications of IXP2400

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

3.2.3
Datasheet
Table 5.
Note: The Media bus is 3.3V LVTTL using globally synchronous (common) clocking. Thus the bus does
SRAM Signals
1. QDR uses a similar compensation scheme as DDR. However, the voltage references are different. The pins S0_ZQ[0] and
Media and Switch Fabric (MSF) Interface
In
CSIX mode.
UTOPIA, POS-PHY, and CSIX specifications. The table shows all the possible signals that could
be used for a particular standard. However, a particular mode within a standard, such as MPHY or
SPHY, will not necessarily use all the signals shown in a column.
not have electrical or clocking compatibility with the CSIX-L1 specification, which is 2.5V
LVCMOS with source synchronous clocking.
Each interface has two clocks; RXCLK01/TXCLK01 is used by the ports associated with bits
[15:0]; RXCLK23/TXCLK23 is used by the ports associated with bits[31:16]. This applies only to
the 4 x 8, 2 x 16, and 1 x 16 + 2 x 8 SPHY modes, and allows each half of the bus to be clocked
independently. In 1 x 32 SPHY, MPHY, or CSIX modes, only RXCLK01/TXCLK01 is used and is
internally routed to all the logic; RXCLK23 and TXCLK23 are tied to ground.
Sn_K[1:0]
Sn_K_L[1:0]
Sn_C[1:0]
Sn_C_L[1:0]
Sn_CIN[1:0]
Sn_CIN_L[1:0]
Sn_DI[15:0]
Sn_PI[1:0]
Sn_DO[15:0]
Sn_PO[1:0]
Sn_BWE_L[1:0]
Sn_RPE_L[1:0]
Sn_WPE_L[1:0]
Sn_A[23:0]
Sn_Vref
Sn_ZQ[1:0]
Total (per channel)
Table
S1_ZQ[0] must each be separately connected to ground through a high precision 50Ω resistor and one 0603 0.1 µF decou-
pling capacitor. The pins S0_ZQ[1] and S1_ZQ[1] should each be separately connected to QDR IO voltage (1.5V) thorough a
high precision 50Ω resistor and one 0603 0.1 µF decoupling capacitor. Place the resistor and capacitor as close to the IXP2400
as possible, within 1.0” of the package. The compensation signal and the VTT trace should be routed with as wide a trace as
possible, minimum of 12 mils wide and isolated from other signals with a minimum of 10-mil spacing.
Signal Name
6, the use of the pins is based on whether or not the port is in UTOPIA, POS-PHY, or
Table 6
shows how the external pin names map to the signal names referenced in the
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
Read Port enable; asserted to start a read.
Positive and negative output clocks. Address, Port
Enable, Data Out are referenced to these clocks.
Positive and negative output clocks used to generate
Sn_CIN[1:0] and Sn_CIN_L[1:0]
Positive and negative clock inputs. They are the feedback
of Sn_C[1:0] and Sn_C_L[1:0].
Data Input bus
Byte parity for data in; PI[1] for DI[15:8], and PI[0] for
DI[7:0]
Data Output bus
Byte parity for data out; PO[1] for DO[15:8], and PO[0] for
DO[7:0]
Byte write enables; asserted to enable writing each byte
during writes.
Write Port enable; asserted to start a write.
Address to SRAMs. Some addresses signals can be
programmed to act as additional port enables (via CSR
control).
HSTL reference voltage
Impedance match
1
Description
Intel
®
IXP2400 Network Processor
Number
16
16
24
81
2
2
2
2
2
2
2
2
2
2
1
2
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