IXP2400 Intel, IXP2400 Datasheet
IXP2400
Specifications of IXP2400
Related parts for IXP2400
IXP2400 Summary of contents
Page 1
... Two industry-standard 32-bit quad-data-rate ■ (QDR) SRAM interfaces — Peak bandwidth of 1.6 GB/s per channel — 100- or 133-MHz SRAM when IXP2400 is running at 400 MHz; 100-, 150- or 200-MHz SRAM when IXP2400 is running at 600 MHz — Hardware support for Linked List and Ring operations — ...
Page 2
... INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The IXP2400 Network Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current errata are available on request. ...
Page 3
... GPIO Signals......................................................................................... 64 3.2.7 Serial Port Signals................................................................................. 65 3.2.8 Clock Signals......................................................................................... 65 3.2.9 Test, JTAG, and Miscellaneous Signals................................................ 65 3.2.10 Configuration Pins ................................................................................. 67 3.2.11 Pin State During Reset.......................................................................... 68 3.3 Power Supply Sequencing ................................................................................. 68 3.3.1 Power-Up Sequence ............................................................................. 68 3.3.2 Power-Down Sequence......................................................................... 68 Datasheet ® Core.............................................................................................. 11 ® Intel IXP2400 Network Processor 3 ...
Page 4
... High-Level Overview of Ballout Functional Groupings Diagram (Ball Side) ........................................................23 10 IXP2400 Network Processor Ball Map (bottom left side) ..................................70 11 IXP2400 Network Processor Ball Map (bottom right side) ................................71 12 PLL Power Supply Connection .......................................................................100 13 SYS_CLK Timing ............................................................................................101 14 PCI Clock Signal AC Parameter Measurements.............................................103 15 PCI Bus Signals ...
Page 5
... Mode 0 Single Read Transfer for Self-Timing Device — SlowPort .................120 42 Boundary Scan General Timing ......................................................................121 43 Boundary Scan Tristate Timing .......................................................................122 44 Boundary Scan Reset Timing..........................................................................122 45 IXP2400 Network Processor General Mechanical Drawing ............................124 Tables 1 DDR Supported Configurations.......................................................................... 17 2 SRAM Controller Configurations ........................................................................ 19 3 Total Memory per Channel................................................................................. 19 4 DDR SDRAM Signals ...
Page 6
... CBus (LVTTL) Driver DC Specifications .......................................................... 117 58 SlowPort, GPIO, and Serial I/O Buffer AC/DC Specifications.......................... 118 59 SlowPort Write Timing...................................................................................... 119 60 SlowPort Read Timing ..................................................................................... 120 61 JTAG DC Specifications................................................................................... 121 62 JTAG AC Specifications................................................................................... 122 63 IXP2400 Network Processor Package Dimensions ......................................... 124 64 IXP2400 Network Processor Die Size.............................................................. 125 6 Datasheet ...
Page 7
... OC-48 (2.5 Gb/s) networking, communications, and data-intensive applications. The IXP2400 has a store and forward architecture that combines a state-of-the-art Intel XScale core with eight multithreaded, independent 32-bit RISC data engines that, when combined, can provide a total of 5 ...
Page 8
... Intel IXP2400 Network Processor Figure 2. IXP2400 Network Processor Functional Signal Groups Diagram 1 Power Supplies Media Switch Fabric Interface Flow- Control DDRAM Interface QDRAM Interface Two of these. "n" VCCA VCC3.3 VCC2.5 VCC1.5 VCC VSS VSSA TXCSRB TXCDATA[3:0] TXCSOF TXCPAR TXCFC RXCSRB ® ...
Page 9
... Figure 3. IXP2400 Network Processor Functional Signal Groups Diagram 2 SYS_RESET_OUT_L Clock Signals TDI_T_SCAN_EN IEEE 1149.1 and Test Signals PLL_DIV_BYPASS Datasheet SYS_RESET_L SYS_CLK ® Intel IXP2400 TCK Network TMS_T_CLK Processor TRST_L T_SYS_REFCLK T_LOAD T_DIAG_CLK THERMDA THERMDC PLL_BYPASS ® Intel IXP2400 Network Processor SP_CLK ...
Page 10
... IXP2400 Network Processor 2.0 Functional Units 2.1 Functional Overview This section provides a brief overview of the IXP2400 Network Processor internal hardware. Figure simple block diagram that shows the device’s major internal blocks. Figure 4. IXP2400 Network Processor Chassis Concept Block Diagram Media Switch ...
Page 11
... Intel XScale core and to take advantage of the performance enhancements to the core. Figure 5 shows the major functional Intel XScale core blocks that surround the ARM* V5TE core. The following sections give a brief, high-level overview of these blocks. Datasheet ® Core ® Intel IXP2400 Network Processor 11 ...
Page 12
... Intel IXP2400 Network Processor ® Figure 5. Intel XScale Core Internal Block Diagram Instruction Cache 32 Kbytes 32 ways Lockable by line Power Management Idle / Drowsy / Sleep JTAG Performance Monitoring Debug Hardware Breakpoints Branch History Table * Arm and StrongARM are registered trademarks of ARM, Ltd. ...
Page 13
... The BTB holds 128 entries. 2.3 Microengines The Microengines (MEs) do most of the programmable per-packet processing in the IXP2400. There are eight MEs, connected as shown in (SRAM, DRAM, MSF, etc.) as well as private connections between adjacent MEs. The MEs provide support for software-controlled multi-threaded operation. Given the disparity in processor cycle times versus external memory times, a single thread of execution will often block, waiting for external memory operations to complete ...
Page 14
... Intel IXP2400 Network Processor Figure 6. Microengine Block Diagram NN_Data_In 640 Local Mem d 128 e GPRs c (A Bank Lm_addr_1 Lm_addr_0 CRC_Remainder CRC Unit (Shift, Add, Subtract, Multiply Logicals, S_Push Local CSRs 2.3.1 Control Store The Control Store is a RAM, which holds the program that the ME executes. It holds 4096 instructions, each of which is 40 bits wide ...
Page 15
... LM supplies operands to the execution datapath as a source, and receives results as a destination. The specific LM location selected is based on the value in one of the LM_Addr Registers which are written by local_CSR_wr instructions. There are two LM_Addr Registers per Datasheet ® Intel IXP2400 Network Processor 15 ...
Page 16
... The DDR Memory Controller controls the off-chip DRAM. The DDR Controller contains the mechanism that allows the other functional units to access the single channel of DRAM present in the IXP2400. DRAM sizes of 64 MB, 128 MB, 512 MB and 1 GB are supported. Single-sided or double-sided DIMMs are supported. The IXP2400 only supports 4-bank DDR devices. ...
Page 17
... Gbit 2.5 SRAM The IXP2400 has two independent SRAM controllers, each of which supports pipelined QDR synchronous static RAM (SRAM) and/or a coprocessor that adheres to QDR signaling. Either controller can be left unused if the application does not need to use its SRAM channels, which are accessible by the Microengines, the Intel XScale core, and the PCI Unit (external bus masters). The memory is logically four bytes (32 bits) wide ...
Page 18
... IXP2400 QDR have on-die termination. The IXP2400 IO driver/receiver can drive up to four QDR device loads. The IXP2400 supports bursts of two SRAM devices. The IXP2400 uses one pair of the Cn/Cn# clocks for read data; the other pair is terminated on the die. The SRAM controller can also be configured to interface to an external coprocessor that adheres to the QDR electricals and protocol ...
Page 19
... Media and Switch Fabric Interface 2.6.1 PHY Modes Supported The Media and Switch Fabric (MSF) Interface connects the IXP2400 to a physical layer device (PHY) and/or a Switch Fabric Interface. MSF consists of the following external interfaces: • Receive and transmit interfaces, each of which can be individually configured for either UTOPIA (Level 1, 2, and 3), POS-PHY (Level 2 and 3) or CSIX protocols ...
Page 20
... Master access (Intel XScale core or Microengine access to PCI target devices) • Three DMA channels • Mailbox and Doorbell Registers for Intel XScale core-to-host communication • PCI arbiter The IXP2400 can be configured to act as PCI central function, or can own the arbitration. 20 Datasheet ...
Page 21
... XPI unit for register reads and writes. 2.8.3 SlowPort The SlowPort is an external interface to the IXP2400 and is used for Flash memory access and 8-, 16-, or 32-bit asynchronous device access. It allows the Intel XScale core to do read/ write data transfers to these slave devices. ...
Page 22
... Intel IXP2400 Network Processor Figure 8. Example SlowPort Connection SP_RD_L SP_WR_L SP_CS_L[0] SP_CS_L[1] SP_A[1:0] SP_AD[7:0] SP_ALE_L SP_CLK ® Intel IXP2400 and ® Intel IXP2800 Network Processors SP_ACK_L 22 CE# D[7:0] 74f377 CP Q[7:0] A[24:18] CE# D[7:0] 74f377 CP Q[7:0] A[17:10] CE# D[7:0] 74f377 CP Q[7:0] A[9:2] OE_L ...
Page 23
... Functional Groupings Diagram (Ball Side) MSF Unpopulated Y1, W1, V1 DDR Unpopulated A1 3.2 Ball Descriptions Grouped by Function This section gives an overview of the IXP2400 IO signals. Detailed definitions and description of the use of signals can be found in chapters of the specification specific to each interface. Datasheet Unpopulated AU[18:20] PCI VCC / VSS Unpopulated A[18:20] ® ...
Page 24
... Place the resistor and capacitor as close to the IXP2400 as possible, within 1.0” of the package. The compensation signal and the VTT trace should be routed with as wide a trace as possible, minimum of 12 mils wide and isolated from other signals with a minimum of 10-mil spacing. ...
Page 25
... The pins S0_ZQ[1] and S1_ZQ[1] should each be separately connected to QDR IO voltage (1.5V) thorough a high precision 50Ω resistor and one 0603 0.1 µF decoupling capacitor. Place the resistor and capacitor as close to the IXP2400 as possible, within 1.0” of the package. The compensation signal and the VTT trace should be routed with as wide a trace as possible, minimum of 12 mils wide and isolated from other signals with a minimum of 10-mil spacing ...
Page 26
... Intel IXP2400 Network Processor Table 6. MSF Data Signals Pin Name I/O RXCLK23 I RXCLK01 I RXENB[3:0] O RXSOF[3:0] I RXEOF[3:0] I RXVAL[3:0] I RXERR[3:0] I RXPRTY[3:0] I RXFA[3:0] I RXADDR[3:0] O RXPFA I RXPADL[1:0] I RXDATA[31:0] I TXCLK23 I TXCLK01 I TXENB[3:0] O TXSOF[3:0] O TXEOF[3:0] O TXERR[3:0] O TXPRTY[3:0] O TXFA[3:0] I TXADDR[3:0] O TXPFA I TXSFA I TXPADL[1:0] O TXDATA[31: TXRCOMP I 26 Type ...
Page 27
... Place the resistor and capacitor as close to the IXP2400 as possible, within 1.0” of the package. The compensation signal should be routed with as wide a trace as possible, minimum of 12 mils wide and isolated from other signals with a minimum of 10-mil spacing. ...
Page 28
... Intel IXP2400 Network Processor Table 7. 1x32 SPHY UTOPIA/POS-PHY Master Mode Port Port 3 (unused) Port 2 (unused) Port 1 (unused) Port 0 RXDATA[31:0] RXPADL[1:0] RXADDR[3:0] MPHY (unused) 28 Master Pin Direction Name RXCLK23 Input unused; tie to ground RXENB[3] Output unused; no connect RXSOF[3] Input unused; tie to ground ...
Page 29
... UTOPIA mode, no connect TXERR[0] Output not used in UTOPIA mode, no connect Output TXFA[0] Input Output not used in UTOPIA mode, no connect Output TXPFA Input unused; tie to ground TXSFA Input unused; tie to ground Output unused; no connect ® Intel IXP2400 Network Processor Notes 29 ...
Page 30
... Intel IXP2400 Network Processor 2x16 SPHY UTOPIA/POS Master Mode Table 8. Port Port 3 (unused) Port 2 RXDATA[31:16] Port 1 Port 0 RXDATA[15:0] 30 Master Pin Direction Name RXCLK23 Input RXENB[3] Output unused; no connect RXSOF[3] Input unused; tie to ground RXEOF[3] Input unused; tie to ground RXVAL[3] Input unused ...
Page 31
... UTOPIA mode, no connect TXERR[0] Output not used in UTOPIA mode, no connect Output TXFA[0] Input Output not used in UTOPIA mode, no connect Output TXPFA Input unused; tie to ground TXSFA Input unused; tie to ground Output unused; no connect ® Intel IXP2400 Network Processor Notes 31 ...
Page 32
... Intel IXP2400 Network Processor 4x8 SPHY UTOPIA/POS-PHY Master Mode Table 9. Port Port 3 RXDATA[31:24] Port 2 RXDATA[23:16] Port 1 RXDATA[15:8] 32 Master Pin Direction Slave Mode Function and Description Name RXCLK23 Input RXENB[3] Output RXSOF[3] Input RXEOF[3] Input not used in UTOPIA mode, tie to ground ...
Page 33
... Output TXCLK23 Input TXENB[2] Output TXSOF[2] Output TXEOF[2] Output not used in UTOPIA mode, no connect TXERR[2] Output not used in UTOPIA mode, no connect Output TXFA[2] Input not used in UTOPIA mode, no connect; not used in Output POS-PHY x8 mode, no connect Output ® Intel IXP2400 Network Processor 33 ...
Page 34
... Intel IXP2400 Network Processor 4x8 SPHY UTOPIA/POS-PHY Master Mode (Continued) Table 9. Port Port 1 TXDATA[15:8] Port 0 TXDATA[7:0] MPHY (unused) TXADDR[3:0] Table 10. 1x16+2x8 SPHY UTOPIA/POS Master Mode Port Port 3 RXDATA[31:24] 34 Master Pin Direction Slave Mode Function and Description Name TXCLK01 Input TXENB[1] ...
Page 35
... UTOPIA mode, tie to ground RXERR[0] Input not used in UTOPIA mode, tie to ground Input RXFA[0] Input not used in POS-PHY Level 3 SPHY mode, tie to ground Input not used in UTOPIA mode, tie to ground Input Output unused; no connect RXPFA Input unused; tie to ground ® Intel IXP2400 Network Processor 35 ...
Page 36
... Intel IXP2400 Network Processor Table 10. 1x16+2x8 SPHY UTOPIA/POS Master Mode (Continued) Port Port 3 TXDATA[31:24] Port 2 TXDATA[23:16] Port 1 (unused) Port 0 TXDATA[15:0] MPHY (unused) TXADDR[3:0] 36 Master Pin Direction Slave Mode Function and Description Name TXCLK23 Input TXENB[3] Output TXSOF[3] Output TXEOF[3] Output ...
Page 37
... Output unused; no connect RXSOF[1] Input unused; tie to ground RXEOF[1] Input unused; tie to ground RXVAL[1] Input unused; tie to ground RXERR[1] Input unused; tie to ground Input unused; tie to ground RXFA[1] Input used only in MPHY-4 direct status mode ® Intel IXP2400 Network Processor Notes 37 ...
Page 38
... Intel IXP2400 Network Processor Table 11. x32 UTOPIA Level 3 MPHY Mode (Continued) Port Port 0 (MPHY) RXDATA[31:0] RXPADL[1:0] RXADDR[3:0] Port 3 (unused) Port 2 (unused) Port 1 (unused) 38 Master Pin Direction Name RXCLK01 Input RXENB[0] Output RXSOF[0] Input RXEOF[0] Input unused; tie to ground RXVAL[0] Input unused ...
Page 39
... RXENB[2] Output unused; no connect RXSOF[2] Input unused; tie to ground RXEOF[2] Input unused; tie to ground RXVAL[2] Input unused; tie to ground RXERR[2] Input unused; tie to ground Input unused; tie to ground RXFA[2] Input unused; tie to ground ® Intel IXP2400 Network Processor Notes Notes 39 ...
Page 40
... Intel IXP2400 Network Processor Table 12. x32 POS-PHY Level 3 MPHY Mode (Continued) Port Port 1 (unused) Port 0 (MPHY) RXDATA[31:0] RXPADL[1:0] RXADDR[3:0] Port 3 (unused) Port 2 (unused) 40 Master Pin Direction Name RXCLK01 Input RXENB[1] Output unused; no connect RXSOF[1] Input unused; tie to ground RXEOF[1] Input unused ...
Page 41
... RXENB[3] Output unused; no connect RXSOF[3] Input unused; tie to ground RXEOF[3] Input unused; tie to ground RXVAL[3] Input unused; tie to ground RXERR[3] Input unused; tie to ground Input unused; tie to ground RXFA[3] Input unused; tie to ground ® Intel IXP2400 Network Processor Notes Notes 41 ...
Page 42
... Intel IXP2400 Network Processor Table 13. 1x32 CSIX Mode (Continued) Port Port 2 (unused) Port 1 (unused) Port 0 (CSIX Rx) RXDATA[31:0] RXPADL[1:0] RXADDR[3:0] TXCDAT[3:0] CBus Tx 42 Master Pin Direction Name RXCLK23 Input unused; tie to ground RXENB[2] Output unused; no connect RXSOF[2] Input unused; tie to ground ...
Page 43
... TXERR[0] Output unused; no connect Output TXFA[0] Input unused; tie to ground Output unused; no connect Output TXPFA Input RXCDAT[5]; used only in x8 CBus mode TXSFA Input RXCDAT[4]; used only in x8 CBus mode Output unused; no connect ® Intel IXP2400 Network Processor Notes 43 ...
Page 44
... Intel IXP2400 Network Processor Table 13. 1x32 CSIX Mode (Continued) Port RXCDAT[3:0] CBus Rx Table 14. x16 UTOPIA Level 2 MPHY-32 + x16 SPHY (UTOPIA or POS-PHY) Mode Port Port 3 (unused) Port 2 (SPHY) RXDATA[31:16] Port 1 (unused) 44 Master Pin Direction Name RXCSOF Input Input RXCPAR Input RXCSRB ...
Page 45
... TXERR[1] Output unused; no connect Output unused; no connect TXFA[1] Input unused; tie to ground ® Intel IXP2400 Network Processor Slave Mode Function and Description MPHY slave mode is not supported RXCLK23 unused; no connect unused; no connect unused; no connect unused; no connect unused; no connect unused; tie to ground ...
Page 46
... Intel IXP2400 Network Processor Table 14. x16 UTOPIA Level 2 MPHY-32 + x16 SPHY (UTOPIA or POS-PHY) Mode (Continued) Port Port 0 (MPHY) TXDATA[15:0] TXADDR[3:0] Table 15. x16 UTOPIA Level 2 MPHY-32 + 2x8 SPHY (UTOPIA or POS-PHY) Mode Port Port 3 (SPHY) RXDATA[31:24] 46 Master Mode Function and Pin Name ...
Page 47
... Input unused, tie to ground Input RXDATA[15:0] TXCSRB Output RXADDR[4] Output RXADDR[3:0] RXPFA Input RXPFA ® Intel IXP2400 Network Processor Slave Mode Function and Description TXCLK23 TXFA[2] TXSOF[2] TXEOF[2] TXENB[2] TXERR[2] TXPRTY[2] unused; tie to ground unused; tie to ground TXDATA[23:16] TXCLK01 unused; tie to ground unused ...
Page 48
... Intel IXP2400 Network Processor Table 15. x16 UTOPIA Level 2 MPHY-32 + 2x8 SPHY (UTOPIA or POS-PHY) Mode (Continued) Port Port 3 (SPHY) TXDATA[31:24] Port 2 (SPHY) TXDATA[23:16] Port 1 (unused) Port 0 (MPHY) TXDATA[15:0] TXADDR[3:0] 48 Master Mode Function Pin Name Direction and Description TXCLK23 Input TXCLK23 TXENB[3] ...
Page 49
... Input unused; tie to ground Input unused; tie to ground RXFA[1] Input unused; tie to ground ® Intel IXP2400 Network Processor Slave Mode Function and Description TXCLK23 unused, no connect unused; tie to ground unused; tie to ground unused; tie to ground unused; tie to ground unused; tie to ground unused ...
Page 50
... Intel IXP2400 Network Processor Table 16. x16 POS-PHY Level 2 MPHY-32 + x16 SPHY (UTOPIA or POS-PHY) Mode (Continued) Port Port 0 (MPHY) RXDATA[15:0] RXADDR[3:0] Port 3 (unused) Port 2 (SPHY) TXDATA[31:16] Port 1 (unused) 50 Master Mode Function and Pin Name Direction Description RXCLK01 Input RXCLK01 RXENB[0] Output ...
Page 51
... Input RXVAL[3] RXERR[3] Input RXERR[3] Input RXPRTY[3] RXFA[3] Input RXFA[3] Input RXDATA[31:24] ® Intel IXP2400 Network Processor Slave Mode Function and Description MPHY slave mode is not supported Slave Mode Function and Description TXCLK23 TXFA[3] TXSOF[3] TXEOF[3] TXENB[3] TXERR[3] TXPRTY[3] unused; tie to ground ...
Page 52
... Intel IXP2400 Network Processor Table 17. x16 POS-PHY Level 2 MPHY-32 + 2x8 SPHY (UTOPIA or POS-PHY) Mode (Continued) Port Port 2 (SPHY) RXDATA[23:16] Port 1 (unused) Port 0 (MPHY) RXDATA[15:0] RXADDR[3:0] 52 Master Mode Function Pin Name Direction and Description RXCLK23 Input RXCLK23 RXENB[2] Output RXENB[2] RXSOF[2] ...
Page 53
... Output TXPADL[0] Output TXDATA[15:0] TXPFA Input TXPFA TXSFA Input TXSFA TXENB[1] Output TXADDR[4] Output TXADDR[3:0] ® Intel IXP2400 Network Processor Slave Mode Function and Description RXCLK23 RXVAL[3] RXSOF[3] RXEOF[3] RXERR[3] RXPRTY[3] RXENB[3] RXDATA[31:24] RXCLK23 RXVAL[2] RXSOF[2] RXEOF[2] RXERR[2] RXPRTY[2] RXENB[2] unused ...
Page 54
... Intel IXP2400 Network Processor Table 18. 1x32 SPHY Slave Mode Port Port 3 (unused) Port 2 (unused) Port 1 (unused) Port 0 RXDATA[31:0] RXPADL[1:0] RXADDR[3:0] MPHY (unused) 54 Master Pin Direction Slave Mode Function and Description Name RXCLK23 Input unused; tie to ground RXENB[3] Output unused; no connect ...
Page 55
... Input RXCLK01 TXENB[0] Output RXVAL[0] TXSOF[0] Output RXSOF[0] TXEOF[0] Output RXEOF[0] TXERR[0] Output RXERR[0] Output RXPRTY[0] TXFA[0] Input RXENB[0] Output RXPADL[1:0] Output RXDATA[31:0] TXPFA Input unused; tie to ground TXSFA Input unused; tie to ground Output unused; no connect ® Intel IXP2400 Network Processor 55 ...
Page 56
... Intel IXP2400 Network Processor Table 19. 2x16 SPHY Slave Mode Port Port 3 (unused) Port 2 RXDATA[31:16] Port 1 Port 0 RXDATA[15:0] 56 Master Pin Direction Slave Mode Function and Description Name RXCLK23 Input TXCLK23 RXENB[3] Output unused; no connect RXSOF[3] Input unused; tie to ground RXEOF[3] Input unused ...
Page 57
... RXVAL[0] TXSOF[0] Output RXSOF[0] TXEOF[0] Output RXEOF[0] TXERR[0] Output RXERR[0] Output RXPRTY[0] TXFA[0] Input RXENB[0] Output RXPADL[0]; Port 0 Output RXDATA[15:0]; Port 0 receive data TXPFA Input unused; tie to ground TXSFA Input unused; tie to ground Output unused; no connect ® Intel IXP2400 Network Processor 57 ...
Page 58
... Intel IXP2400 Network Processor Table 20. 4x8 SPHY Slave Mode Port Port 3 RXDATA[31:24] Port 2 RXDATA[23:16] Port 1 RXDATA[15:8] 58 Master Pin Direction Slave Mode Function and Description Name RXCLK23 Input TXCLK23 RXENB[3] Output TXFA[3] RXSOF[3] Input TXSOF[3] RXEOF[3] Input TXEOF[3] RXVAL[3] Input TXENB[3] ...
Page 59
... TXFA[2] Input RXENB[2] Output unused; no connect Output RXDATA[23:16]; Port 2 receive data TXCLK01 Input RXCLK01 TXENB[1] Output RXVAL[1] TXSOF[1] Output RXSOF[1] TXEOF[1] Output RXEOF[1] TXERR[1] Output RXERR[1] Output RXPRTY[1] TXFA[1] Input RXENB[1] Output RXDATA[15:8]; Port 1 receive data ® Intel IXP2400 Network Processor 59 ...
Page 60
... Intel IXP2400 Network Processor Table 20. 4x8 SPHY Slave Mode (Continued) Port Port 0 TXDATA[7:0] MPHY (unused) TXADDR[3:0] Table 21. 1x16+2x8 SPHY Slave Mode Port Port 3 RXDATA[31:24] Port 2 RXDATA[23:16] 60 Master Pin Direction Slave Mode Function and Description Name TXCLK01 Input RXCLK01 TXENB[0] Output ...
Page 61
... TXFA[3] Input RXENB[3] Output RXDATA[31:24]; Port 3 receive data TXCLK23 Input RXCLK23 TXENB[2] Output RXVAL[2] TXSOF[2] Output RXSOF[2] TXEOF[2] Output RXEOF[2] TXERR[2] Output RXERR[2] Output RXPRTY[2] TXFA[2] Input RXENB[2] Output unused; no connect Output RXDATA[23:16]; Port 2 receive data ® Intel IXP2400 Network Processor 61 ...
Page 62
... Intel IXP2400 Network Processor Table 21. 1x16+2x8 SPHY Slave Mode (Continued) Port Port 1 (unused) Port 0 TXDATA[15:0] MPHY (unused) TXADDR[3:0] Table 22. CBus Pinout Pin Name TXCDATA[3:0] TXCDATA[7:4] TXCSOF TXCSRB TXCFC TXCPAR RXCDATA[3:0] RXCDATA[7:4] RXCSOF RXCSRB RXCFC RXCPAR 62 Master Pin Direction Slave Mode Function and Description ...
Page 63
... IXP2400 is arbiter/host. Bus grant output to external master 0 when this chip is IO arbiter/host; grant input to the IXP2400 from external arbiter when not a host. Bus grants to external master 1, used when the IXP2400 is O arbiter/host Indication that a 64-bit data phase is desired. During reset, IO driven low by the system to indicate 64-bit capability. ...
Page 64
... The PCI_RCOMP pin should be connected to ground through external a 24Ω ±1% resistor and one 0603 0.1 µF decoupling capacitor. Place the resistor and capacitor as close to the IXP2400 as possible, within 1.0” of the package. The compensation signal should be routed with as wide a trace as possible, minimum of 12 mils wide and isolated from other signals with a min- imum of 10-mil spacing ...
Page 65
... Transmit data from the UART I/O Description System Clock I This is the core PLL reference clock; nominally 100 MHz System reset input I If the IXP2400 externally hosted PCI system this is connected to PCI_RST_L Reset out O IXP2400 output to reset the other board devices Table ® IXP2400 Network Processor ...
Page 66
... For normal operation, connect to 0. PLL Divider Bypass 0 - Core PLL divider block is not bypassed system board this pin should be held low. If set high, the IXP2400 may not operate properly. Indicates that power has reached a certain level. Keep I pulled-up for normal operation. Analog clock power 3 ...
Page 67
... These pins are tied statically high or low through a resistor to provide configuration information into the IXP2400 at reset. For all but CFG_RST_DIR, these pins are used for other purposes after reset. For those pins the configuration information is sampled at the deassertion edge of reset. The values sampled can be read in the Strap_Options Register ...
Page 68
... D_Vref 6. Sn_Vref The power supplies for the IXP2400 should be brought controlled sequence. The delay between the power-up of the power supplies should less (min is 50 µs); there is no dependency between the sequence of the 1.5V and 2.5V power-on. 1. The 3.3V must be brought up before the1.3V 2 ...
Page 69
... SlowPort Clock Behavior During Reset In IXP2400 A0 silicon, when the SYS_RESET_L or the PCI_RST_L is asserted, the SP_CLK drives out the clock signal at the same frequency as the SYS_CLK, but 180 degrees out of phase with the SYS_CLK. After the de-assertion of both SYS_RESET_L (and PCI_RST_L if CFG_RSTDIR = 1), the SP_CLK will drive out the clock signal at half of the SYS_CLK frequency after approximately three SYS_CLK cycles the programmed frequency ...
Page 70
... Intel IXP2400 Network Processor 3.4 Ball Information Figure 10. IXP2400 Network Processor Ball Map (bottom left side) Bottom View D_BA[1] VSS VCC2.5 ECC[3] DQS[ VSS ECC[7] DQ[37 VCC2.5 ECC[6] DQS[8] D_ VSS D_DM[8] 5 ECC[ VCC2.5 DQ[25] ECC[4] D_A[4] D_A[3] VSS VCC2.5 D_A[11] ...
Page 71
... Figure 11. IXP2400 Network Processor Ball Map (bottom right side) Bottom View VCC3.3 TXDATA TXDATA 2 [27] [21] TXENB 3 VCC3.3 [2] TXDATA 4 [22] TXERR VCC3.3 5 [2] TXDATA TXDATA 6 [31] [23] TXSOF VCC3.3 7 [2] TXEOF TXDATA 8 [2] [26] 9 VSS VCC VCC VCC VCC VSS 10 11 VSS VCC ...
Page 72
... IXP2400 Network Processor 3.5 Ball List Tables Table 30 defines the signal types on the ball list. ) Table 30. IXP2400 Network Processor Signal-Type Abbreviations Ball Abbreviation VCC3.3 VCC2.5 VCC1.5 VCC VSS VCCA VSSA PD OD DNC 3.5.1 Balls Listed in Alphanumeric Order by Signal Name The following ball locations are not associated with a signal, therefore are not listed in Y37, W37, V37, AU[18:20], and A[18:20] ...
Page 73
... E16 D_DQS[0] B13 D_DQS[1] E14 D_DQS[2] C9 D_DQS[3] E8 D_DQS[4] C2 D_DQS[5] H2 D_DQS[6] K3 D_DQS[7] M6 D_DQS[8] B4 D_ECC[0] H10 D_ECC[1] H11 D_ECC[2] B5 D_ECC[3] B2 D_ECC[4] C6 IXP2400 Network Processor Ball Signal Name Location D_ECC[5] F9 D_ECC[6] A4 D_ECC[7] A3 D_RAS_L E2 D_RCOMP[0] G1 D_RCOMP[1] H1 D_RCVENIN_L P5 D_RCVENOUT_L P4 D_VREF[0] A12 D_VREF[1] P1 D_WE_L E1 GPIO[0] AF31 GPIO[1] ...
Page 74
... IXP2400 Network Processor Ball Signal Name Location PCI_AD[24] AP22 PCI_AD[25] AT22 PCI_AD[26] AU22 PCI_AD[27] AL21 PCI_AD[28] AM21 PCI_AD[29] AP21 PCI_AD[3] AM28 PCI_AD[30] AR21 PCI_AD[31] AT21 PCI_AD[32] AP37 PCI_AD[33] AR37 PCI_AD[34] AT37 PCI_AD[35] AM36 PCI_AD[36] AN36 PCI_AD[37] AP36 PCI_AD[38] AT36 PCI_AD[39] AM37 ...
Page 75
... F27 S0_A[8] F28 S0_A[9] G24 S0_BWE_L[0] B33 S0_BWE_L[1] H27 S0_C[0] F29 S0_C[1] A34 S0_C_L[0] E29 S0_C_L[1] A32 S0_CIN[0] E21 IXP2400 Network Processor Ball Signal Name Location S0_CIN[1] C22 S0_CIN_L[0] D20 S0_CIN_L[1] F20 S0_DI[0] H23 S0_DI[1] F23 S0_DI[10] B21 S0_DI[11] F19 S0_DI[12] ...
Page 76
... IXP2400 Network Processor Ball Signal Name Location S0_K_L[1] C32 S0_PI[0] F21 S0_PI[1] C23 S0_PO[0] F36 S0_PO[1] A36 S0_RPE_L[0] D30 S0_RPE_L[1] C33 S0_VREF A24 S0_WPE_L[0] C34 S0_WPE_L[1] C37 S0_ZQ[0] J30 S0_ZQ[1] H29 S1_A[0] U36 S1_A[1] T35 S1_A[10] R35 S1_A[11] R36 S1_A[12] R30 ...
Page 77
... TXEOF[2] Y8 TXEOF[3] W7 TXERR[0] AM1 TXERR[1] AM3 TXERR[2] Y5 TXERR[3] V6 TXFA[0] AE8 TXFA[1] AF3 TXFA[2] AD4 TXFA[3] AC7 TXPADL[0] AF4 IXP2400 Network Processor Ball Signal Name Location TXPADL[1] AF6 TXPFA AF1 TXPRTY[0] AM2 TXPRTY[1] AN2 TXPRTY[2] W3 TXPRTY[3] V2 TXRCOMP AC1 TXSFA AE6 TXSOF[0] AK4 ...
Page 78
... IXP2400 Network Processor Ball Signal Name Location VCC AA27 VCC W27 VCC U27 VCC R27 VCC N27 VCC L27 VCC J27 VCC AK26 VCC AH26 VCC AF26 VCC AD26 VCC AB26 VCC Y26 VCC V26 VCC T26 VCC P26 VCC M26 ...
Page 79
... L11 VCC J11 VCC AK10 VCC AH10 VCC AF10 VCC AD10 VCC AB10 VCC Y10 VCC V10 VCC T10 IXP2400 Network Processor Ball Signal Name Location VCC P10 VCC M10 VCC K10 VCC AJ9 VCC AG9 VCC AE9 VCC AC9 VCC ...
Page 80
... IXP2400 Network Processor Ball Signal Name Location VCC1.5 H31 VCC1.5 AD30 VCC1.5 AB30 VCC1.5 Y30 VCC1.5 V30 VCC1.5 T30 VCC1.5 P30 VCC1.5 M30 VCC1.5 K30 VCC1.5 G30 VCC1.5 E30 VCC1.5 B30 VCC1.5 H28 VCC1.5 E28 VCC1.5 B28 VCC1.5 H26 VCC1.5 E26 VCC1 ...
Page 81
... M29 VSS K29 VSS G29 VSS D29 VSS A29 VSS AR28 VSS AL28 VSS AJ28 VSS AG28 VSS AE28 IXP2400 Network Processor Ball Signal Name Location VSS AC28 VSS AA28 VSS W28 VSS U28 VSS R28 VSS N28 VSS L28 VSS ...
Page 82
... IXP2400 Network Processor Ball Signal Name Location VSS AD25 VSS AB25 VSS Y25 VSS V25 VSS T25 VSS P25 VSS M25 VSS K25 VSS G25 VSS D25 VSS A25 VSS AR24 VSS AL24 VSS AJ24 VSS AG24 VSS AE24 VSS AC24 ...
Page 83
... U12 VSS R12 VSS N12 VSS L12 VSS J12 VSS AK11 VSS AH11 VSS AF11 VSS AD11 VSS AB11 IXP2400 Network Processor Ball Signal Name Location VSS Y11 VSS V11 VSS T11 VSS P11 VSS M11 VSS K11 VSS G11 VSS ...
Page 84
... IXP2400 Network Processor Ball Signal Name Location VSS AG8 VSS AC8 VSS W8 VSS V8 VSS U8 VSS T8 VSS R8 VSS P8 VSS U7 VSS T7 VSS R7 VSS P7 VSS M7 VSS J7 VSS F7 VSS C7 VSS AR6 VSS AL6 VSS AG6 VSS AC6 VSS W6 VSS U6 VSS T6 VSS R6 VSS U5 VSS T5 VSS R5 VSS ...
Page 85
... AA21 VCC AA22 VSS AA23 VCC AA24 VSS AA25 VCC AA26 VSS AA27 VCC AA28 VSS AA29 VCC IXP2400 Network Processor Table 32: A1, Y1, W1, V1, Ball Signal Name Location AA30 S1_ZQ[0] AA31 VSS AA32 S1_DO[7] AA33 S1_DO[10] AA34 VSS AA35 S1_RPE_L[0] AA36 ...
Page 86
... IXP2400 Network Processor Ball Signal Name Location AB24 VCC AB25 VSS AB26 VCC AB27 VSS AB28 VCC AB29 VSS AB30 VCC1.5 AB31 S1_ZQ[1] AB32 S1_DO[0] AB33 VCC1.5 AB34 S1_DO[4] AB35 S1_DO[5] AB36 VCC1.5 AB37 S1_DO[8] AC1 TXRCOMP AC2 VSS AC3 MSF_CLK_BYPASS ...
Page 87
... VCC AG20 VSS AG21 VCC AG22 VSS AG23 VCC AG24 VSS AG25 VCC AG26 VSS AG27 VCC AG28 VSS IXP2400 Network Processor Ball Signal Name Location AG29 VCC AG30 TCK AG31 TRST_L AG32 SERIAL_RX AG33 TDO AG34 GPIO[6] AG35 SYS_RESET_L AG36 ...
Page 88
... IXP2400 Network Processor Ball Signal Name Location AH30 T_DIAG_CLK AH31 VSS AH32 VCC3.3 AH33 VSS AH34 VCC3.3 AH35 PLL_DIV_BYPASS AH36 SYS_RESET_OUT_L AH37 VSS AJ1 VCC3.3 AJ2 TXDATA[2] AJ3 VCC3.3 AJ4 TXDATA[3] AJ5 VCC3.3 AJ6 RSVD[0] AJ7 VCC3.3 AJ8 TXADDR[1] AJ9 VCC ...
Page 89
... VCC3.3 AN26 PCI_AD[14] AN27 VCC3.3 AN28 PCI_AD[4] AN29 VCC3.3 AN30 PCI_PAR64 AN31 VCC3.3 AN32 PCI_AD[55] AN33 VCC3.3 AN34 PCI_AD[46] IXP2400 Network Processor Ball Signal Name Location AN35 VCC3.3 AN36 PCI_AD[36] AN37 VCC3.3 AP1 RXPRTY[0] AP2 RXDATA[3] AP3 RXDATA[2] AP4 RXDATA[5] AP5 ...
Page 90
... IXP2400 Network Processor Ball Signal Name Location AP36 PCI_AD[37] AP37 PCI_AD[32] AR1 RXEOF[1] AR2 VSS AR3 RXDATA[6] AR4 VSS AR5 RXDATA[13] AR6 VSS AR7 RXDATA[4] AR8 VSS AR9 RXENB[3] AR10 VSS AR11 RXDATA[23] AR12 VSS AR13 RXDATA[20] AR14 VSS AR15 RXFA[3] ...
Page 91
... S0_K_L[1] C33 S0_RPE_L[1] C34 S0_WPE_L[0] C35 S0_DO[8] C36 S0_DO[5] C37 S0_WPE_L[1] D1 D_A[10] D2 VCC2.5 D3 D_DQ[32] D4 D_BA[0] D5 VSS D6 D_DM[3] IXP2400 Network Processor Ball Signal Name Location D7 D_DQ[26] D8 VCC2.5 D9 D_A[8] D10 D_DQ[18] D11 VSS D12 D_DQ[21] D13 D_DQ[14] D14 VCC2.5 D15 D_DQ[20] D16 D_DQ[13] ...
Page 92
... IXP2400 Network Processor Ball Signal Name Location E8 D_DQS[3] E9 VSS E10 D_DQ[28] E11 D_DQ[24] E12 VCC2.5 E13 D_DM[2] E14 D_DQS[1] E15 VSS E16 D_DQ[9] E17 D_DQ[6] E18 VCC2.5 E19 S0_DI[13] E20 VCC1.5 E21 S0_CIN[0] E22 VCC1.5 E23 S0_DI[2] E24 VCC1.5 E25 S0_A[10] E26 VCC1 ...
Page 93
... D_CS_L[1] K2 VCC2.5 K3 D_DQS[6] K4 D_DQ[55] K5 VSS K6 D_DM[6] K7 D_CAS_L K8 VCC2.5 K9 VSS K10 VCC K11 VSS K12 VCC IXP2400 Network Processor Ball Signal Name Location K13 VSS K14 VCC K15 VSS K16 VCC K17 VSS K18 VCC K19 VSS K20 VCC K21 VSS K22 ...
Page 94
... IXP2400 Network Processor Ball Signal Name Location L14 VSS L15 VCC L16 VSS L17 VCC L18 VSS L19 VCC L20 VSS L21 VCC L22 VSS L23 VCC L24 VSS L25 VCC L26 VSS L27 VCC L28 VSS L29 VCC L30 S1_PI[0] ...
Page 95
... VSS T10 VCC T11 VSS T12 VCC T13 VSS T14 VCC T15 VSS T16 VCC T17 VSS T18 VCC IXP2400 Network Processor Ball Signal Name Location T19 VSS T20 VCC T21 VSS T22 VCC T23 VSS T24 VCC T25 VSS T26 ...
Page 96
... IXP2400 Network Processor Ball Signal Name Location U20 VSS U21 VCC U22 VSS U23 VCC U24 VSS U25 VCC U26 VSS U27 VCC U28 VSS U29 VCC U30 S1_BWE_L[0] U31 VSS U32 S1_K_L[0] U33 S1_A[4] U34 VSS U35 S1_C_L[1] U36 S1_A[0] ...
Page 97
... Ball Signal Name Location Y28 VCC Y29 VSS Y30 VCC1.5 Y31 S1_DO[9] Y32 S1_DO[12] Y33 VCC1.5 Y34 S1_DO[13] Y35 S1_PO[1] Y36 VCC1.5 Datasheet IXP2400 Network Processor 97 ...
Page 98
... Intel IXP2400 Network Processor 4.0 Electrical Specifications This chapter specifies the following electrical behavior of the IXP2400: • Absolute maximum ratings • DC values and AC timing specifications for the following: — PCI I/O Unit — QDR — DDR SDRAM — C Bus — POS-PHY and CSIX — ...
Page 99
... Totals 14.19 1. Values presented include core and I/O. 2. 400-MHz (B Stepping) IXP2400 devices should use a 1.1V core power supply; 600-MHz IXP2400 devices can only use a 1.3V core power supply. 3. QDR and DDR I/O values include power consumption from termination. The values in ...
Page 100
... IXP2400 and the SRAM chips to be close to each other, termination can be removed or termination resistance can be increased. For instance, on boards that demonstrate good signal integrity and have the IXP2400 and SRAM chips placed within two inches of each other, there may be no need for termination. ...
Page 101
... SYS_CLK slew rate 1. These specifications apply only to SYS_CLK and are very preliminary estimates. 2. 0.2 x VCC3.3 to 0.6 x VCC3.3. 3. When the IXP2400 powers up, the reference clock should start running as soon as possible. 4.2.2 PCI I/O Unit This section specifies the following electrical behavior for the PCI I/O Unit. ...
Page 102
... Intel IXP2400 Network Processor • Absolute maximum ratings • DC specifications • AC timing specifications 4.2.2.1 PCI Absolute Maximum Ratings Table 40. Absolute Maximum PCI Ratings Parameter Maximum voltage applied to signal pins Supply voltage (I/O), VCC3.3 The power specifications listed in • PCI Bus Frequency (PCI_CLK MHz. ...
Page 103
... VSS – 0.74V VCC3.3 + 0.74V VSS – 0.74V VCC3.3 + 0.74V T cyc T high low V t3 Parameter PCI_CLK cycle time PCI_CLK high time PCI_CLK low time 1 PCI_CLK slew rate ® Intel IXP2400 Network Processor Maximum Duration A9817-02 Minimum Maximum Unit — — ns 1.5 4 V/ns 103 ...
Page 104
... Intel IXP2400 Network Processor Table 45. 33-MHz PCI Clock Signal AC Parameters Symbol T cyc T high T low — 1. 0.3 VCC3.3 to 0.6 VCC3.3. Figure 15. PCI Bus Signals PCI_CLK Outputs Inputs Note 0.4 VCC3.3 for 3.3 volt PCI signals test 4.2.2.6 PCI Bus Signals Timing Table 46 ...
Page 105
... I/O is VCC1.5/2 - 0.2 tristated) Note 1 VCC1.5 x .75 - 0.1 |IOL| ≤ 0.1 mA (when the I/O is VCC1.5/2 - 0.2 tristated) Note 2 VCC1.5/4 - 0.1 — 1.4 — 0.7 ® Intel IXP2400 Network Processor Minimum Maximum Unit — ns — — — ...
Page 106
... The setup time is measured with 1V/ns input slew rate. Figure 17 illustrates the timing goals for the IXP2400 QDRII interface. For QDR necessary to delay the input clock appropriately to acheive the required setup and hold time. For example, for QDR at 100 MHz, delay the input clock by 2.1 ns compared to data. The clock will be shifted by 2 ...
Page 107
... DDR input high voltage, DC Datasheet t cyde cyde Table 51 Parameter 0.48 x VCC2.5 VCC2.5 x .75 - VCC2.5/4 - 0.15 VDREF + 0.15 ® Intel IXP2400 Network Processor B1257-01 lists the AC parameters. Minimum Maximum Unit 0.52 x VCC2.5 VCC2.5 x .75 + 0.15 0.15 VCC2.5 -10 +10 µA — VDREF - 0.15 — ...
Page 108
... Intel IXP2400 Network Processor Table 50. DDR SDRAM DC Parameters for 100/150 MHz (Continued) Symbol VIL (AC) DDR input low voltage, AC VIH (AC) DDR input high voltage DDR input/output pin capacitance IO Table 51. DDR SDRAM AC Parameters for 100/150 MHz Symbol Tck D_CK period Tck (high) ...
Page 109
... Valid Data Valid Data Valid Data t HD ® IXP2400 Network Processor 100 MHz Unit Max Min Max — 4.78 — ns 7.08 8.99 10.61 ns 1.96 — 2.94 ns 10.31 14.17 15.47 (tCKlow= (tCKlow= 2 ...
Page 110
... Intel IXP2400 Network Processor Figure 19. Data and Error Correction Valid Before and After Data Strobe (Write Operation) D_DQS D_DQ, D_ECC Figure 20. Write Preamble Duration D_DQS Figure 21. Write Postamble Duration D_DQS Figure 22. Command Signals Valid Before and After Clock Rising Edge ...
Page 111
... Figure 25. Clock Cycle Time D_CK_L[2:0] D_CK[2:0] Figure 26. Skew Between Any System Memory Differential Clock Pair D_CK_Lx D_CKx D_CKy D_CK_Ly Datasheet t t CKE_VB CKE_VA Valid Data t t CS_VB CS_VA Valid Data SKEW ® Intel IXP2400 Network Processor A9824-03 A9825-03 A9826-01 A9827-01 111 ...
Page 112
... Intel IXP2400 Network Processor Figure 27. Clock High Time D_CK_L[2:0] D_CK[2:0] Figure 28. Clock Low Time D_CK_L[2:0] D_CK[2:0] Figure 29. Data Strobe Falling Edge Output Access Time to Clock Rising Edge D_CK_L[2:0] D_CK[2:0] D_DQS Figure 30. Data Strobe Falling Edge Output Access Time from Clock Rising Edge ...
Page 113
... Figure 33. Clock Rising Edge Output Access Time to Output Clock Falling Edge D_CK_L[2:0] D_CK[2:0] D_A[12:0], D_BA, D_RAS_L, D_CAS_L, D_WE_L D_RCVENOUT_L Datasheet ® Intel Write CMD t DQSS Write CMD t POE Read CMD t D_RCVENOUT_L IXP2400 Network Processor 0.5xVCC2.5 A9832-01 0.5xVCC2.5 A9833-01 0.5xVCC2.5 A9834-01 113 ...
Page 114
... This section describes the parameters for the MSF Interface. These parameters apply whether the bus is configured to carry either POS Level 2/SPI-3 packets/cells or UTOPIA 1/2/3 CSIX C-Frames. The MSF Interface can operate at a maximum of 133 MHz with a 600-MHz IXP2400, and at a maximum of 104 MHz with a 400-MHz IXP2400. 114 ...
Page 115
... VSS – 1V VSS – 0.74V VCC3.3 + 0.74V T cyc T high Vih Vil Minimum Typical 0 — 2.4 — 0 — -0.2 — ® Intel IXP2400 Network Processor Min Max 2.0V — — 0.8V 2.4V — — 0.5V -10 µA +10 µA — Overshoot Maximum Duration VCC3 ...
Page 116
... Input setup time to RXCLK23 TXsu23 T Input hold time from RXCLK23 TXh23 The IXP2400 supports the IXF6048 UTOPIA Level 3 (single 64-bit, 32-bit, or quad 8-bit), Level 2 (single 8/16-bit), and Level 1 (quad 8/16-bit) interface modes. Figure 38 and Figure 39 interface, 32/16/8-bit databus, two clock cycle decode-response delay and no high-impedance outputs ...
Page 117
... Txsu Txh Valid Input Parameter Condition — — Ioh = -8 mA Iol = 8 mA 0<Vin<VCC3.3 — ® Intel IXP2400 Network Processor Valid Output 0.5xVCC3.3 Valid Input A9841-01 0.5xVCC3.3 Valid Input A9842-01 Minimum Maximum 2.0V — — 0.8V 2.4V — 0.4V -10 µA +10 µ ...
Page 118
... AC and DC parameters for the SlowPort and GPIO. The GPIO can be used with appropriate software in I for the DC and AC characteristics. The serial port consists of TXD, RXD, which are asynchronous relative to any device outside the IXP2400. Table 58. SlowPort, GPIO, and Serial I/O Buffer AC/DC Specifications Symbol ...
Page 119
... Intel IXP2400 Network Processor 9:2 17:10 tsu tpw (ns) (ns) Max Min Max Min — — — — — ...
Page 120
... Intel IXP2400 Network Processor Figure 41. Mode 0 Single Read Transfer for Self-Timing Device — SlowPort t t CO_rise CO_fall 0 2 P_CLK SP_CLK SP_ALE_L SP_CS_L[1:0] SP_WR_L SP_RD_L SP_A[1:0] SP_AD[7:0] 9:2 17:10 SP_ACK_L t co Table 60. SlowPort Read Timing tco rise (default) (ns) External Signals Max ...
Page 121
... VCC3.3 + 0.3 — -0.3 Output(s) disabled, -10.0 0V ≤ Vin ≤ VDD IOH = -2.0 mA 2.4 IOL = 2.0 mA — 3.0 Tbscl Tbsls Tbslh Tbsoh Tbsod Tbsss Tbssh Tbsdh Tbsdd ® IXP2400 Network Processor Maximum Unit Notes 1 V 0.8 V — µA +10.0 — — 0 3.6 V ...
Page 122
... Intel IXP2400 Network Processor Figure 43. Boundary Scan Tristate Timing tck tdo Data Out Figure 44. Boundary Scan Reset Timing ntrst tms Table 62. JTAG AC Specifications Symbol Tbscl TCK low period Tbsch TCK high period Tbsis TDI, TMS setup to tck Tbsih TDI, TMS hold from tck ...
Page 123
... Data output disable time applies when the boundary scan logic is used to disable the output drivers. 8. TCK may be stopped indefinitely in either the low or high phase. Datasheet Parameter Minimum Typical — — 30 — 10 — 10 — ® Intel IXP2400 Network Processor Maximum Unit Notes — ns — — 123 ...
Page 124
... Intel IXP2400 Network Processor 5.0 Mechanical Specifications 5.1 Package Dimensions The IXP2400 is contained in a 1356 package, as shown in described in Table 63. Figure 45. IXP2400 Network Processor General Mechanical Drawing E F1 TOP VIEW Table 63. IXP2400 Network Processor Package Dimensions Symbol 124 Pin #1 Corner C A3 ...
Page 125
... Table 63. IXP2400 Network Processor Package Dimensions (Continued) Symbol NOTE: Measurements in millimeters. Table 64. IXP2400 Network Processor Die Size X 17.20 NOTE: Measurements in millimeters. Datasheet 1356 BGA Minimum Maximum 37.45 37.55 37.45 37.55 33.4 33.6 33.4 33.6 1.00 0.750 0.750 Y Z 18.67 0.815 ® ...
Page 126
... Intel IXP2400 Network Processor This page is intentionally left blank. 126 Datasheet ...