IXP2400 Intel, IXP2400 Datasheet - Page 18

• Manufacturer Part Number: IXP2400
• Manufacturer: Intel

Specifications of IXP2400

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel
2.5.1
18
Figure 7. Clock Configuration
®
IXP2400 Network Processor
Each of the two QDR ports are QDR- and QDRII-compatible. Each port implements the “_K” and
“_C” output clocks as an input and their inversions. The “_C” clocks are used for reading SRAM
data and the “_K” clocks are used for writing SRAM data. Extensive work has been performed to
control the impedance within the IXP2400 for IXP2400-initiated signals that drive QDR parts. The
receivers of IXP2400 QDR have on-die termination.
The IXP2400 IO driver/receiver can drive up to four QDR device loads. The IXP2400 supports
bursts of two SRAM devices. The IXP2400 uses one pair of the Cn/Cn# clocks for read data; the
other pair is terminated on the die.
The SRAM controller can also be configured to interface to an external coprocessor that adheres to
the QDR electricals and protocol.
SRAM Controller Configurations
Each channel has enough address pins (24) to support up to 64 MB of SRAM. The SRAM
controllers can directly generate multiple port enables (up to four pairs) to allow for depth
expansion. Two pairs of pins are dedicated for port enables. Smaller RAMs use fewer address
•
•
•
Samsung* 36-Mb QDRII x9 K7R320982M-FC20 or 36-Mb QDRII x18 K7R321882M-FC20
SRAM
IDT* IDT71T6280H 9-Mb pipelined QDR SRAM burst of 2 (512K x 18)
Cypress* CY7C1302V25 9-Mb pipelined SRAM with QDR architecture (512K x 18)
Note: Leave CQ/CQ# as NC.
Intel®
IXP2400
Network
Processor
C1n/C1n#
C2n/C2n#
C1/C1#
C2/C2#
K1/K1#
K2/K2#
Termination
Termination
Vtt
Vtt
50
50
Ω
Ω
Clam-shelled SRAMs
C/C#
C/C#
K/K#
K/K#
C1/C1#
C2/C2#
C/C#
C/C#
Package Balls
Package Balls
Datasheet
B0059-01