MT9VDDF3272Y-40BK1 Micron Technology Inc, MT9VDDF3272Y-40BK1 Datasheet - Page 12

• Manufacturer Part Number: MT9VDDF3272Y-40BK1
• Description: MODULE DDR SDRAM 256MB 184RDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT9VDDF3272Y-40BK1

• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.62A
• Number Of Elements: 9
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 400MT/s
• Features: -
• Package / Case: 184-RDIMM
• Lead Free Status / Rohs Status: Compliant

Table 11:
PDF: 09005aef8082c948/Source: 09005aef807d56a1
ddf9c32_64x72.fm - Rev. C 10/08 EN
Parameter/Condition
Operating one device bank active-precharge current:
(MIN);
cycle; Address and control inputs changing once every two clock cycles
Operating one device bank active-read-precharge current: Burst = 4;
t
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-
down mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle.
VIN = VREF for DQ, DQS, and DM
Active power-down standby current: One device bank active; Power-
down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank;
Active precharge;
inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
Operating burst read current: Burst = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle;
Operating burst write current: Burst = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
cycle
Auto refresh burst current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
READs; (burst = 4) with auto precharge,
Address and control inputs change only during active READ or WRITE
commands
RC =
t
t
t
RC (MIN);
CK =
CK =
t
CK =
t
t
CK (MIN); IOUT = 0mA
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
t
t
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock
I
Values are for MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
CK =
CK =
DD
t
CK =
t
Specifications and Conditions – 512MB
RC =
t
CK (MIN); CKE = (LOW)
t
CK (MIN); CKE = LOW
t
CK (MIN); IOUT = 0mA; Address and control inputs
t
RAS (MAX);
t
CK =
t
RC =
256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
t
CK (MIN); DQ, DM, and DQS
t
RC (MIN);
t
t
RFC =
RFC = 7.8125µs
t
t
CK =
CK =
t
t
RC =
12
RFC (MIN)
t
t
CK (MIN);
CK (MIN);
t
RC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
1,395
1,665
1,710
1,755
3,105
4,050
-40B
495
405
540
45
99
45
Electrical Specifications
©2002 Micron Technology, Inc. All rights reserved.
1,170
1,440
1,485
1,575
2,610
3,645
-335
405
315
450
45
90
45
1,035
1,305
1,305
1,215
2,520
3,150
-265
360
270
405
45
90
45
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA